资源列表
LS164
- 用verilog原因实现LS164移位寄存器(Implementation of the LS164 shift register with Verilog)
subtraction floating point
- subtract two number floating point (32 bit)
Altera_verilog_lcd12864
- FPGA采用Altera_verilog实现lcd12864中文显示-FPGA using Altera_verilog achieve lcd12864 Chinese display
ft_top
- 用quartus6原理编辑方式写的简易频率计我自己的实验来的 保证能使请您认真查看谢谢 -quartus6 principle used to write the editorial summary Cymometer my own experiments can guarantee you Thank you seriously View
Detection-Algorithm
- vhdl for edge détection prewi-vhdl for edge détection prewitt
alu
- verilog 编写的 可综合的ALU单元 可执行加减与或非 5种运算-verilog prepared by the ALU unit can be integrated with non-executable plus or minus five kinds of computing
IIC
- fpga实现的IIC通信的例程，注释很详细-fpga implementation of serial communication routines, comments in great detail
send_middle
- 智能温控 18b20 1302 报警 12864-My English is not good。。。
haoleba
- VHDL言语实现的24制时钟,可整点报时,还有闹钟等功能.-VHDL language to achieve the 24 system clock can be the whole point of time, there is an alarm clock functions.
GPIOsimulateUART
- 此代码是用8051普通的GPIO口来模拟串口-This code is to use the GPIO port 8051 to simulate an ordinary serial port
shizhongsheji
- 基于UP3borad开发板的时钟设计，可校时，设置闹钟等-Clock design based on UP3borad the development board, can the school, set the alarm
priority
- Priority encoder in VHDL.