资源列表
5
- 用VHDL语言实现电子钟-Using VHDL language electronic bell
HD_7279_b
- hd7279在fpga控制下由按键控制数码管的程序，可以使得数码管循环显示，有闪烁功能-hd7279 under the control of the fpga digital control by the key control procedures, can make the digital control loop shows that flash function
DE2_LCM_CCD
- DE2 CCD数码相机源代码，下载即可使用。方便学习。-DE2 CCD digital camera source code, you can use to download. Facilitate learning.
UART2
- 基于SPARTAN-3E的与计算机的异步串行通信，可根据需要更改波特率等等。-SPARTAN-3E based on the asynchronous serial communication with the computer, according to the need to change the baud rate and so on.
VGA
- 使用标准VHDL实现的VGA协议，可在CPLD或者FPGA上实现视频扩展-use VHDL to implement VGA protocol, which can be used in CPLD or FPGA.
crc_testbench
- 此为crc测试台文件。主要环境是modelsim。适用于初学者-This is the crc test bench file. Main environment is modelsim. Apply to beginners
hw1
- Using the schematic Design Entry Method, design a logic circuit that has two 2-bit inputs X and Y, a 1-bit input CinOrBin, and a 1-bit control input SubAddn. When the control input SubAddn is ‘0’, the logic circuit behaves as a 2-bit adder ( X + Y +
Project
- verilog code for misr
LCD1602Display
- FPGA中LCD1602驱动开发设计，软件quartusII6.0，verilog-LCD1602 driver in the development of FPGA design, software quartusII6.0, verilog
9927416JpegDecoder
- altera nios处理器快速入门，对研究NIOS的人员很有帮助-altera nios processor, quick start, the staff very helpful for research NIOS
Verilog_USB_IN
- USB in 模型，作为输入，包括基于Altera的工程、源码、固件，使用Verilog-USB in model, as input, including the Altera-based project, source code, firmware, Verilog
RS232
- RS232的FPGA通讯程序，用的是VHDL语言写的，非常好用-RS232 communication program of the FPGA, using the VHDL language, very easy to use