资源列表
shuzizhong1
- 数字钟包含时分秒计时，还有时钟和分钟的校正，同时还能显示日期。(Digital clock contains a time when every minute, and the clock and the minute correction, but also display the date.)
signalgenerater
- 一个简单的多种信号的发生器 包括正玄，锯齿，阶梯等，使用时用quartus 4.0以上版本打开-a simple multiple signal generator including Shogen, sawtooth, the ladder, when used with the above version 4.0 Quartus open
FastEllipticCurveCryptographyonFPGA
- FastEllipticCurveCryptographyonFPGA
38504873-pll
- Introduction In 2004 Octavian Florescu created the UW ASIC group. At that time, the analog subgroup of the UW ASIC group was involved in the design of a PLL. The topology of that PLL, which is now referred to as Phase Locked Loop Version 1, i
ViterbiFPGA
- 探讨了CDMA 数字移动通信中的差错控制问题, 研究用约束度K = 9 的卷积编码 和最大似然V iterbi 译码的差错控制方案. 在V iterbi 译码算法中, 提出了原位运算度量、保 存路径转移过程和循环存取幸存路径等方法, 能有效地减少存储量、降低功耗, 使得K = 9 的V iterbi 译码算法可在以单片XC4010 FPGA 为主的器件上实现, 其性能指标符合CD2 MA 数字移动通信IS 95 标准要求. 文中给出了实测的算法性能, 讨论了FPGA 具体实现
reg8b
- Registrador de 8 bits
EPCS_datasheet
- FPGA的EPCS专用datasheet-FPGA-specific datasheet EPCS
89
- 几种verilog语言的分频计设计，初学者适用-Several verilog language points frequency plan design, for beginners
ps2_mouse_demo
- 在FPGA芯片上进行串口鼠标应用的良好例程-Good routine serial mouse applications on the FPGA chip
chufaqi
- 用vhdl编写的N位除法器，适合初学者学习和编程- written in VHDL a N divider, suitable for beginners to learn and program
lock2
- 使用VHDL语言，实现了一个四位二进制串行密码锁-VHDL language to achieve a serial lock
signalgenerator
- 使用VHDL编写的函数信号发生器，该模块使用文本输入-Written using the VHDL function signal generator, the module uses text input