资源列表
Final
- 乘法器,模拟两个0-99的数相乘，将结果显示在7段数码管上，可FPGA平台烧制~-Multiplier, two 0-99 multiplying the number of analog, the results displayed in the 7-segment digital tube, may FPGA platform firing ~
ad976
- FPGA实现AD976的自动采样的Verilog HDL程序，所采用的是AD976的模式一，已调试成功-AD976 FPGA to realize the automatic sampling of the verilog HDL program, the is AD976 model a, already debugging success
FPGA
- 利用FPGA来实现一个简单的医疗呼叫系统，使用语言VERILOG-FPGA to realize the use of a simple medical call system, the use of language VERILOG
FPGADDS
- dds，FPGA波形发生器,波表，接受，发送-dds, FPGA waveform generator, wave form, to receive, send
XC3S700_7SEG_Test
- 红色飓风3S700AN开发板LED数码管测试例程-Red Hurricane 3S700AN development board seg LED test code
encoder_clk
- 精确实现奇数分频，将FPGA开发板提供的25MHZ时钟分频为1MHZ，内含测试文件(Accurate realization of odd frequency division, the FPGA development board provides 25MHZ clock frequency divided into 1MHZ, containing test files)
First_test_Blinking_LEDs
- my first tuto on de1 bored vhdl code blink leds my first tuto on de1 bored vhdl code blink leds my first tuto on de1 bored vhdl code blink leds -my first tuto on de1 bored vhdl code blink leds my first tuto on de1 bored vhdl code blink leds my first
TFT
- 3.5寸TFT FPGA驱动程序,2C8驱动扫描TFT屏实现色条-TFT DV for FPGA
Add_sub_struc
- 8位加减器，八位减法器与加法器，用过一个控制端可以自由变换，采用移位加法方式，用途广泛，利用减法位补码加法的理论实现。-8 addition and subtraction, eight subtractor and adder, used a control terminal can freely change the using Shift addition, a wide range of uses, the use of subtraction complement addition t
Full_Adder
- Full Adder for Xilinx
A8255V4
- A8255.ZIP contains code that implement a modified 8255 Peripherial Port Controller. The code is written in verilog and project is made for XILINX ISE.
booth_mult
- ＦＰＧＡ的ｖｒｉｌｏｇ ＨＤＬ代码，布尔乘法器-FPGA-vrilog HDL code, the Boolean multiplier