资源列表
qiangdaqi.rar
- 用verilog编写的抢答器,当主持人宣布“开始比赛”,系统初始化,选手进入“抢答状态”。当某一选手首先按下抢答开关时,相应的指示灯亮,此时抢答器不再接受其他输入信号。电路具有累计分控制(分别用4个4位选手的积分——十六进制数),由主持人控制“加分”。“加分”加分完毕,开始下一轮抢答。电路还可以设有回答问题时间控制。 ,Answer using Verilog prepared, and when the host announced the " start game" , t
vhdlpiano
- 这是一个用vhdl写的电子琴的小程序(整个工程文件),希望对大家有所帮助
VHDLMQP04
- VHDL Implementation of the JPEG-LS Algorithm
liushuideng
- 基于XILINX公司FPGA的流水灯代码,采用硬件描述语言VHDL-XILINX' s FPGA-based water lamp code, using hardware descr iption language VHDL
modelsim
- 教程学习MODELSIM,江西介绍了怎么运用改仿真软件进行各种仿真和优化设计-A detailed information of MODELSIM
final-2
- 数字信号系统设计,使用VHDL进行模拟信用卡的使用,存钱,取钱-Digital signal system design, simulation using VHDL use of credit cards, to save money. . .
LED-LCD
- 8051MCU GPIO aboutLED-LCD-8051MCU about Display
LCD
- LCD驱动器的完整代码,详细verilog编程-LCD drive complete code, verilog detailed programming
ipI2C
- IP核的设计与验证,使用I2C进行FPGA与FPGA之间进行通信-Design and verification of IP cores, using I2C communication between the FPGA and the FPGA. .
uart_lcd_display_XUP
- Uart串口通信程序,PC机向FPGA的串口发送数据,FPGA的串口收到数据后回传到PC机,同时显示在lcd屏。-Uart serial communication program: The serial port of PC sends data to the FPGA. After the serial port of FPGA receives the data, FPGA sends the received data back to the PC, simultaneously dis
ethernet_tri_mode_latest.tar
- ethernet_tri_mode_latest.tar.gz源代码-ethernet_tri_mode_latest.tar.gz source code
uart
- 一个在Quartus 12.0 Web版下做的Uart收发例子,具备基本的收发功能。-Uart transceivers example, with a in Quartus 12.0 Web version under the basic functions of the transceiver.
