资源列表
NC-pulse-generator
- 电工电子实验（数控脉冲信号发生器）详细讲解课件-Electronics Experiment (NC pulse generator) explain in detail Courseware
jiaotongdeng
- 运用 vhdl语言编写 交通灯控制器的设计-jiaotongdeng
A-VHDL-Primer---Bhasker
- VHDL exaples project from CPLD or FPGA
FPGA
- fpga 实例源码FPGA片上硬件乘法器的使用-fpga sourcecode
i2c
- I2C控制器的FPGA实现，为verilog语言。-The I2C controller FPGA implementation verilog language.
lcdasegaled
- lcd显示 跑马灯显示 七段数码管计时 12232F是一种内置8192个16*16点汉字库和128个16*8点ASCII字符集图形点阵液晶显示器,它主要由行驱动器/ 列驱动器及128×32全点阵液晶显示器组成。可完成图形显示,也可以显示7.5×2个(16×16点阵)汉字.与外部CPU接口采用并行或串行方式控制。-lcd display Seven-Segment LED Display Marquee is a built-in timing 12232F 8192 16* 16 points
PL2
- 用CPLD实现的数字频率计，功能齐全，经过验证，绝对好使。-CPLD implementation of digital frequency meter, fully functional
SOPC
- 这是基于DE2平台的sopc实验,对初学者很具有参考价值-This is based on the DE2 platform sopc experiment is a reference value for beginners
DDS
- 这是一个用EP2C5T144的FPGA制作的DDS信号发生器，输出信号波形可变，幅度可调，缺点是信号频率略低，带有电路图-This is a used EP2C5T144 FPGA produced DDS signal generator, the output signal waveform variable adjustable amplitude, the disadvantage is that the signal frequency is slightly lower, with
CNT10-START.rar
- 十进制计数器的设计的源代码 verilog语言 ,conter10
VerilogTutorial
- verilog tutorial for beginners
DDS1
- DDS信号发生器，能产生多种波形，正玄波，三角波，方波，频率可调，相位可调