资源列表
FIFO2
- 用verilog HDL语言编写的fifo存储器源文件 -Using Verilog language HDL FIFO memory source file
AD9280-
- 进阶实验_15_AD[AD9280] ：采集模拟输入，电压动态显示在数码管 - 副本-Advanced Experimental _15_AD [AD9280]: acquire analog input voltage dynamic display digital tube- copy
VHDL.rar
- 正弦信号发生器具有频率调节功能。采用VHDL编程实现。,Sinusoidal signal generator with a frequency adjustment function. Using VHDL programming.
CPU
- 用VHDL设计的cpu 用微指令方法设计 通过rom查表的方式进行设计-Cpu design with VHDL designed by microinstructions way through the design of look-up table rom
i2c_latest.tar
- i2c协议(i2c)
counter-and-timer
- T触发器的计数器和计时器，希望能帮到大家-T trigger counters and timers, hope to help you
VGA_CTL
- 通过VGA显示一个汉字，用verilog编写，属于进阶实验-Through a VGA display Chinese characters, written with verilog, are advanced experimental
I2C
- K2FPGA开发板实验教程——I2C协议说明及verilog实现读写I2C器件，中文内涵代码，验证可用。-K2FPGA development board test tutorial- I2C protocol descr iption and verilog read and write I2C devices, Chinese connotation code to verify availability.
vga
- 用VHDL写的vga串口实验，已经调试通过。-Vga serial experiments have been written using VHDL debugging through.
ReadDpram
- 读DPRAM状态机，Quartus -DPRAM read state machine, Quartus II
juchibo
- verilog实现输出锯齿波形，已经通过DA芯片验证通过-verilog to achieve the output sawtooth waveform, has passed through the DA chip verification
lmf
- 在ISE下，FPGA产生线性调频信号，并且产生信号的参数可调(In ISE, the FPGA generates a linear frequency modulation signal, and the parameters of the signal are adjustable.)