资源列表
superdigitalclock
- 这是基于FPGA开发板BASYS2的一个智能数字时钟，可以分3种模式：分钟，秒，百分之一秒。通过button切换模式并显示在数码管上-This is based on the FPGA development board BASYS2 a intelligent digital clock, can divide three patterns: the minutes and seconds, of a second.Through the button switch mode and in d
multiply_shift_add
- 基于移位相加运算的乘法器设计，完整的设计工程文件在multiply_shift_add文件夹下-Multiplier design based on shift and add operations, complete design engineering file multiply_shift_add file folder
traffic_light_3_09
- 数码管驱动、HC595驱动、VHDL、分频器-Digital tube drive, HC595 drive, VHDL, divider
RECEIVER
- 此程序为基于OFDM的802.11a的接收端的VERILOG代码，包含所有模块。-This program is VERILOG code receiving end 802.11a OFDM-based, including all modules.
V4LwipUseMb
- 在AVNET的V4FX12开发板上使用MB实现网络的例子，可作为千兆网开发或者其他使用Xilinx芯片的朋友参考。-AVNET board in the development of V4FX12 example of using the MB network can be developed as Gigabit Ethernet or other friends using Xilinx chip reference.
shuzidianzizhongsheji
- 数字电子钟设计，分模块设计，秒分时模块，用vhdl写的-Digital electronic clock design, sub-module design and second time-sharing module, written with vhdl
kechengsheji
- 拨码开关控制点阵显示十进制数 内含VHDL PDF等文件-DIP switches control the dot matrix display contains a decimal number, such as VHDL PDF file
Receiver
- 该程序是整个OFDM接收机的程序，希望对做这方面的朋友用些帮助，也希望朋友们和我一起探讨OFDM收发信机。-The program is the whole OFDM receiver process, hope to do in this area with some friends to help and also hope that friends and I explore OFDM transceiver.
Receiver
- OFDM的接收器的FPGA实现，通信中具有重要作用-OFDM receiver of the FPGA implementation, communication plays an important role in
ofdmbaseband
- the OFDM PHY is adaptive therefore it supports multiple schemes BPSK, QPSK, 16-QAM and 64-QAM for data carriers’ modulation. The constellation diagrams are gray mapped and shows the magnitudes I and Q (In-phase and Quadrature) components of e
hfjhtb
- 整个ofdm系统的每一步功能的verilog实现-The ofdm system as a whole every step functions verilog implementation