资源列表
ip-cores-video_controller_jpeg_encoder
- ip-cores-video_controller_jpeg_encoder
czcgl
- 出租车管理系统,为本人毕业设计. 还请大家多多指教了
add32
- 32位加法器，基于vhdl语言，主要用于测试算法-32-bit adder, based on the vhdl language, mainly used for testing algorithms
lcd_12864
- 本历程使用FPGA根据LCD12864的时序图编译成功的可以显示汉字、字母数字的VHDL程序-The process of using the FPGA timing chart compiled according to LCD12864 success can display Chinese characters, alphanumeric VHDL program
EP3C40EDA_Example27
- 选用CycloneIII系列芯片EP3C40F780C8，button_test 按键测试实验代码-CycloneIII，EP3C40F780C8，button_test code
用串口DMA方式接收发送数据
- 在STM32板子与电脑串口助手进行通信,用串口的DMA方式,先接收,再发送到PC端,可以连续接收,通过按键一次发送.(In the STM32 board and computer serial assistant for communication, using the serial port DMA way, first receive, and then sent to the PC terminal, you can receive continuously, sent through
Quartus_IIjiaocheng
- 数字电路设计工具教程，详细说明其用法和许多历程-Digital circuit design tools Tutorials
DSP-Algorithm-logic
- 它是一部很好的学习数字信号处理算法逻辑的书籍，文中先介绍了数字信号处理的算法，之后讲解了用Verilog HDL的学习和算法编写-It is a good learning logic digital signal processing algorithms book, the paper introduces the first digital signal processing algorithms, and then explained the study and use of Veril
6_USB_to_SDHC_Lab
- altera max10 USB demo，使用了phy，把开发板配置成U盘模式-altera max10 USB demo，using PHY device，design a U pan
fengpingPfifo
- 基于DE0平台实现不同时钟下采集8位AD芯片采样速率，并进行发送。采用的是FIFO模块。-8 AD chip sampling rate based on DE0 platform different clock collection and send. FIFO module.
dtsmg
- 此代码运用的verilog语言实现对于动态数码管的编写，在动态数码管上显示0~7这几个数字。-This code using the verilog language realization for dynamic digital tube compiling, and in dynamic digital tube display 0 ~ 7 this a few Numbers
67506256DDS
- 基于FPGA 的直接数字频率合成信号发生器(DDS)设计-FPGA-based direct digital synthesizer signal generator (DDS) design. Pdf