资源列表
Quartus
- Quartus使用教程,个人觉得还比较不错。对本人的帮助还蛮大的-Quartus Tutorial use, personal feel that is still relatively good. I had quite a big help
CPU16
- 自己用VHDL写的16位的CPU，在学校的课程上通过了测试。-Own use VHDL to write a 16-bit CPU, in school curriculum passed the test.
pinglvjiFPGA
- 基于等精度原理的频率计verlog代码,被测频率在1HZ到10MHZ误差百分比相同。-Based on the principle of the frequency of such precision code
VHDL-AUTOMATIC-FAIR-COLLECTION
- 基于VHDL的地铁售票系统，可以实现票数输入以及找零功能-Metro ticketing system based VHDL, can enter the number of votes and the change function
cadenceveriloglanguageandsimulationcourse
- cadence verilog lanaguage and simulation course
dianzhen
- 这是一个基于FPGA开发实验箱的汉字点阵显示的Verilog HDL程序，经过实验调试验证过的 -This is an FPGA-based development of experimental box character dot-matrix display Verilog HDL procedures, through experimental testing verified
cic_cq
- 在altera平台用verilog硬件描述语言实现cic抽取滤波，包含完整的工程代码，已经仿真通过，可以直接用于实践-In the Altera platform using Verilog hardware descr iption language CIC decimation filter, contains the complete project code, has been adopted by simulation, can be used directly in practice
seg7_controller
- 七段译码器循环显示，并打包为IP核，可在其他程序中使用，已调试，可用。-Seven segment display decoder loop, and packaged as IP cores, can be used in other programs have debugging available.
shift
- 此源代码的功能是对一个二进制数进行移位操作-failed to translate
ask
- 这个是基本q2和dspbuilder的ask实现，是做实验的好参考资料。-This is the basic realization of q2 and dspbuilder the ask is a good reference experiment.
sigcpld
- 用51单片机控制ARIC429的地址计算的CPLD代码，CPLD为XC95108-MCU with 51 address ARIC429 calculated CPLD code, CPLD to XC95108
VHDL-clock
- VHDL的程序设计模块，很有用那个，密码锁。-for vhdl！！