资源列表
verilog实例 [43项]
- 一些采用verilog描述的数字功能模块,有常见的同步异步FIFO,RAM等模块,适合新手学习(Some digital function modules described by Verilog, such as synchronous asynchronous FIFO and ram, are suitable for novice learning)
QuartusII原理图输入法设计VHDL组合逻辑电路设计VHDL时序逻辑电路设计
- QuartusII原理图输入法设计VHDL组合逻辑电路设计VHDL时序逻辑电路设计三个实验
AD转换VHDL
- 控制ADC0809芯片的AD转换功能的VHDL程序
DDR2_SDRAM操作时序
- DDR2_SDRAM操作时序,介绍的很详细,不错(DDR2? SDRAM operation sequence, very detailed introduction, very good)
vivado2018+IPs
- Xilinx Vivado 2018 License File
基于FPGA的多路同步脉冲发生器设计1
- 采用FPGA(现场可编程门序列)编写VHDL语言设计多路同步脉冲发生器,对信号进行分频处理,实现四路信号相位相差T/16和T/8的延迟相位输出,实现的四路脉冲与传统的脉冲同步器不同,它具有高集成度,高通用性,容易调整和高可靠性等特点。(Using FPGA (field programmable gate sequence) to write VHDL language to design multi-channel synchronous pulse generator, to divide
FPGA实现Jpeg压缩,和视频采集程序
- FPGA实现Jpeg压缩,和视频采集程序(Zynq - Main - register access Mio)
ac620_calculator_key_board
- 基于Verilog编写的计算器,使用矩阵键盘输入数据,使用数码管显示运算过程和结果,基于小梅哥AC620开发板验证通过(The calculator based on Verilog uses matrix keyboard to input data and digital tube to display the operation process and results. The development board based on little mac620 passed the veri
基2的快速傅里叶变换
- 基2的快速傅里叶变换,可定制位宽和点数的基2的FFT变换模块
基2的快速傅里叶变换
- 基2的快速傅里叶变换,可定制位宽和点数的基2的FFT变换模块
Xilinx
- 2020 XILINX Vivado ISE IP License最全最可靠License获取方式。 LDPC, CPRI, Turbo, Polar, JESD204B/C HDMI1.4/2.0, MIPI CSI-2, MIPI DSI AXI CAN AXI USB2.0 SD Card Host Reed-Solomon Decoder/Encoder 10G Enthernet MAC 25G Enthernet MAC 40G Enthernet MA
basketball_24time1
- 该文档主要是用verilog语言实现篮球24秒计时器,这是我做的数字电子技术课程的一次大作业。 里面为整个文件夹,解压之后可在Quartus13.0上直接运行。(This document mainly uses Verilog language to realize basketball 24 second timer, which is a big assignment of digital electronic technology course I do. It contains the