资源列表
UART
- 自己总结的UART的设计及分析，已在实际工程中应用到，并且带有源代码和仿真代码，总结的文档，非常有用。(My summary of the design and analysis of UART, has been applied in practical engineering, and with source code and simulation code, summary of the document, very useful.)
VHDL101
- A part of VHDL design book
CPU
- CPU VHDL based design
MUT32
- MUT32 pipelined VHDL code
fpga-hash-table-master
- FPGAs based hash table
adder
- 进位加法，实现两个数的相加功能，可以扩展到多位数相加(Carry addition, to achieve the addition function of two numbers, can be extended to the number of add)
i2c_slave
- Verilog i2c slave rtl + testbench 仿真ok(Verilog i2c slave rtl + testbench)
i2c_master
- verilog i2c master rtl+testbench 转自特权同学(verilog i2c master rtl+testbench)
uart_test
- 基于FPGA 的sparten-6 AX-309片内串口uart通信例子(FPGA sparten-6 AX-309 uart connection example)
Verilog_HDL教程
- verilog HDL入门语法资料，适合FPGA初学者的一本电子书。(Verilog HDL Introductory Grammar data)
QSYS
- sopc系统，应用Qsys的应用程序，以便于新手学习(To achieve real-time operation of the system, to help newcomers just to understand)
bubblesort
- 根据ASMD图设计验证冒泡排序算法。给出设计程序及时序仿真结果，含纸质报告。(According to the ASMD diagram design, verify the bubble sorting algorithm. Give the design procedure and the simulation result in time, including paper report.)