资源列表
piano
- 电子琴 原创 作业 VHDL 采用计数器分频，内含简单儿歌数首，爱迪克ＥＤＡ实验箱，有数码管与ＬＥＤ显示，采用键盘式输出，两行，中音高音。(Electronic piano original work VHDL, using counter frequency division, contains a few simple nursery rhyme, Edik EDA experimental box, there are digital tube and LED display, usin
Songer
- 梁祝音乐演奏，用fpga器件驱动小扬声器构成一个乐曲演奏电路(Butterfly Lovers music performance)
jesd204
- xilinx平台 jesd204核例化使用示例(Xilinx platform jesd204 core example of the use demo)
CMI
- CMI编码原理图，可以通过对m5随即序列进行编码和解码(CMI is designed for m5 random list, which is should in the project, and it can decode it and get the original m5 list)
pn10
- 用verilog生成11级的pn序列，Xilinx平台(Generating 11 levels of PN sequences with Verilog)
121114156PCIE_DMA_DDR3_verilog_design
- 基于FPGA的pcie dma设计，可参考应用。(FPGA based PCIe DMA design, you can refer to the application.)
扩频通信的Verilog工程
- 扩频通信的Verilog工程，对从事无线通信的工程人员有参考作用。(Spread spectrum communication Verilog project, engaged in wireless communications engineering staff reference.)
FIFO_RAM
- 同步FIFO_RAM的设计及其testbench(8 bit SYN FIFO module fifo_v(clk,rst,wen,ren,full,empty,data,q);)
zhangnan11
- 一个基于FPGA的洗衣机正反转定时控制器，可以在开发板上实现控制和显示功能(A FPGA based washing machine is reverse timing controller, you can control and display functions on the development board)
shuzizhong1
- 数字钟包含时分秒计时，还有时钟和分钟的校正，同时还能显示日期。(Digital clock contains a time when every minute, and the clock and the minute correction, but also display the date.)
shouhuojixi1
- 自动邮票售货机，选择要购买的邮票，直接投入硬币就可以购买。(Automatic stamp vending machine, select the stamps to buy, directly into coins can buy.)
adder
- 能够实现单精度浮点加法运算。输入引脚有：第一运算数，第二运算数，复位信号，时钟信号。输出信号有：运算结果，运算完成标志。(To achieve a single precision floating-point addition operations)