资源列表
ARM JTAG Debug
- 这篇文章主要介绍 ARM JTAG 调试的基本原理。 基本的内容包括了 TAP (TEST ACCESS PORT) 和 BOUNDARY-SCAN ARCHITECTURE 的介绍， 在此基础上， 结合 ARM7TDMI 详细介绍了的 JTAG 调试原理。(OPEN-JTAG Development Group.)
JTAG_Example0_Verilog
- 一个Verilog的JTAG程序例子，包括完整的说明文档和源文件。(tap_top.v This file is part of the JTAG Test Access Port (TAP) http://www.opencores.org/projects/jtag/ Author(s): Igor Mohor (igorm@opencores.org))
zhong5
- Basys2开发板上烧写后，可在LCD1602显示屏上动态显示年月日时分秒和温度值，并且可以手动设置闹钟和温度上下限，越限报警。(Basys2 development board programmer, can dynamically display the date when the minutes and seconds and temperature on the LCD1602 screen, and you can manually set the alarm clock and th
键盘实验文件_modify
- 键盘数据读取，并显示在数码管上，速度可达到100M频率(Read the keyboard data, and display on the digital tube, frequency speed can reach 100M)
time_zh_4
- 按键选择状态，6位数码管显示，有闹钟、整点报时功能，时间可调(Button selection status, 6 digital display, alarm clock, the whole point timekeeping function, time adjustable)
UART1
- 可直接用于zedboard上的串口通信，利用zynq7000的pl部分实现一个简单的UART串口通信(Can be used directly on the zedboard serial communication, the use of zynq7000 PL part of the realization of a simple UART serial communication)
booth
- 16位booth乘法器的实现：先将被乘数的最低位加设一虚拟位。开始虚拟位变为零并存放于被乘数中，由最低位与虚拟位开始，一次判定两位，会有4种判定结果。(The 16 bit booth multiplier to achieve: first the least significant bit is added with a virtual position. Start a virtual becomes zero and stored in the multiplicand, startin
hola mundo2
- hat the image I was created by convolving a true image with a % point-spread function PSF and possibly by adding noise. The algorithm % is optimal in a sense of least mean square error between the % estimated and the true images
qam16 modulator
- QAM16 MODULATOR VERILOG CODE ON FPGA
fir filter design
- FIR FILTER DESIGN IN VERILOG ON FPGA
reconf. router code xylinx
- design and fpga implementation of Routing algorithm for NOC
16x 16 vedic mulbit
- vedic 16x16 design and teshbench fully working codes..