资源列表
fsk_modulation
- 实现FSK调制功能，改变输入波形就可以有不同的输出-Achieve FSK modulation capabilities, to change the input waveform can have different output
SpWIF
- spacewire 总线收发接口源代码，VHDL，适用于Xilinx，测试FPGA：XC3S1000FTG256-4C-spacewire bus transceiver interface, the source code, VHDL, applicable to Xilinx, testing FPGA: XC3S1000FTG256-4C
mm1
- 基于随机数组中的最大值与最小值的选择器，可自由设定输出时钟和数组大小-Maximum and Minimum Value Selector
Xil3SD1800A_MIG
- 基于xc3sd1800afg676的开发板的DDR2的控制器的IPCORE，提供完整的代码和UCF。系统时钟频率为125Mhz。-The development board based on xc3sd1800afg676 DDR2 controller of IPCORE, provide a complete code and UCF. System clock frequency of 125Mhz.
lshifter
- 有时为了处理数据，需要将寄存器中的各位数据在移位控制信号作用下，依次向高位或向低位移动1位成为移位寄存器-Sometimes in order to process the data, you need to register in the role of data in the shift control signals, the order of low to high or to move one into the shift register
ddspsk
- 产生13位barker码，还有2spk信号产生-13-bit barker code, 2spk signal generation
counter
- 用verilog写的计数器，可用于分频等多种功能。已经调试成功很好用-Written with verilog counter, can be used for frequency and other functions. Has been very good success with debugging
paomadeng
- 用verilog写的跑马灯，已经调试成功，很好用-Use verilog to write marquees, has been debugged, useful
ddscore
- dds基本结构，能进行相位累加，具有调相功能-dds basic structure of the phase can accumulate, with the phase modulation function
adc5510
- 使用VHDL语言编写的A/D转换程序，可在FPGA平台使用-Using the VHDL language in the A/D conversion process can be used in the FPGA platform
PERL_PROGRAM
- perl program for generating test vector and veryfying test vector useful for VHDL design verification
fpga_and_spi
- fpga实现spi接口，包括主机和从机程序-FPGA， SPI