资源列表
multi8
- 8位乘法器-multi8
S9_LED_RUN
- 这是一段用VHDL语言编写的LCD的启动程序-S9_LED_RUN
S1_38yima
- 3-8译码器的VHDL语言实现的源程序代码-3-8Decoder
SOPC_UART
- altera公司的ep1c240c8n，串口调试程序vhdl\nios ii8.0代码等-altera company ep1c240c8n, serial debugger vhdl \ nios ii8.0 code. .
BuildingtheCPUdatapath
- Building the CPU datapath
HA
- Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.
Verilog
- 通过本文章的学习能够使我们设计一些简单的逻辑电路和系统。很快我们就能过渡到设计相当复杂的数字逻辑系统。-To learn through this article, will enable us to design some simple logic circuits and systems. Soon we will be able to transition to the design of complex digital logic systems.
asdasdasdasd
- 基于quartus的3-8译码器,可作为大型系统的译码器模块-Based on quartus a 3-8 decoder can be used as large-scale system decoder module
verilog_example
- verilog例子资源，对于初学者很有帮助。-verilog examples of resources are very useful for beginners.
FPGA
- fpga测温的框图和源码 希望能帮到大家 没有测试 紧供参考-fpga vhdl
Advanced_verilog_coding
- 高级verilog编程实现讲义，全英文讲义 -Senior verilog programming lecture notes, handouts in English
alu_project
- ALU using VHDL project