资源列表
eeprom
- EEPROM模块源代码，希望对大家有用，方便交流-EEPROM model
flash_writer
- Flash 读写verilog代码，希望对大家有用，便于交流-flash writer and reader
commutionbetweenFPGAand8951F
- 单片机与ＦＰＧＡ的通信 功能 :单片机控制写FPGA一字节数据 单片机控制写FPGA一字节数据时钟 (注意读写数据端口可复用,也可分用) 单片机控制发送数据端口 -MCU and FPGA communication functions: SCM control FPGA to write a byte of data SCM control FPGA to write a byte of data clock (Note that the read and write
clkdiv
- 初学者一个比较容易入门的FPGA verilog 二分频实验。-Relatively easy for beginners to get into a FPGA verilog two-way experiment.
VHDL
- 介绍VHDL编程的资料，很详细，值得收藏-vhdl
20096411m5349886
- 本程序实现任意占空比产生，已经在easyfpga030综合过-This procedure generated to achieve an arbitrary duty cycle
Verilog
- basic verilog for students
82_Examples_for_VHDL_and_Verilog_code
- 包括VHDL、verilog在内的各种设计实例，是学习硬件描述语言的帮手。共有82个实验例子，涉及各种语法规则。-82 VHDL, verilog test case, involving a variety of grammatical rules. which is you learn the HDL language helper.
UARTE
- 用VHDL语言编写的串口通讯模块，可以实现发送和接受功能。-A UART module writen in VHDL.
JmsQuartzTest
- JmsQuartzTest JmsQuartzTest -JmsQuartzTest JmsQuartzTest JmsQuartzTest
au
- 基于APB总线的uart控制器，包括源码和vcs脚本-UART controller based on AMBA APB
ask
- 设计的一个ask调制器与解调，输入时钟clk，输入开始信号start，输入基带数据信号din及输出已调信号ask-Designed to ask a modulator and demodulator, the input clock clk, enter a start signal start, enter the baseband data signal din and the output modulated signal ask