资源列表
fir_filter
- 使用Verilog编程实现的分布式FIR滤波器源码，经过调试能够完成功能-Distributed programming using the Verilog source code FIR filters, after a debugging feature to complete
uart16550_latest[1].tar
- 开源UART IP核16550，该IP核兼容16550 UART，具有Modem功能，完全可编程的串行接口具有可设置的字符长度、奇偶校验、停止位以及波特率生成器。-Open-source UART IP core 16550, the IP core is compatible with 16550 UART, with Modem function, fully programmable serial interface can be set up with a character lengt
exchange
- 实现三层电梯控制，有楼层记忆功能，有故障处理形式。total文件下是具体的实现形式-Elevator control to achieve the three-tier
yufafenxiqi
- 该程序能求出任意给定的文法的所有非终极符和终极符的first集，所有非终极符的follow集，所有语句的select集，能求出能导空的非终极符集合。给定任意字符串该程序能判定出是否能接受。由于空符号不好输入，在程序中用到空符号全部用@表示。-The program can calculate any given grammar of all non-ultimate breaks and the ultimate symbol of the first set, all non-ultimate
cardTEL
- 基于verilog-hdl的卡式电话电路，编译环境quartusII72，经下载仿真通过。-Verilog-hdl cassette based on telephone circuits, build environment quartusII72, has been downloaded by simulation.
AutoWashing
- 基于verilog-hdl的洗衣机自动控制电路，经下载仿真测试通过 附带时钟分频器-Verilog-hdl-based automatic control circuit of the washing machine, after download the simulation test
VHDL-Cookbook
- a vhdl book it is so nice and usefu-a vhdl book it is so nice and usefull
Alarm_Cloc188508552005
- vhdl files for alarm digital clock
15example
- 夏宇闻老师的verilog数字系统设计教程书上的所有例题的源程序15章-XIA Yu-Wen teachers verilog digital system design tutorial books, all of the source code Example Chapter 15
18example
- 夏宇闻老师的verilog数字系统设计教程书上的所有例题的源程序18章-XIA Yu-Wen teacher' s verilog digital system design tutorial books, all of the source code Example Chapter 18
16example
- 夏宇闻老师的verilog数字系统设计教程书上的所有例题的源程序16章-XIA Yu-Wen teacher' s verilog digital system design tutorial books, all of the source code Example Chapter 16
2example
- 夏宇闻老师的verilog数字系统设计教程书上的所有例题的源程序-XIA Yu-Wen teacher' s verilog digital system design tutorial books, all the Example of the source code