资源列表
22
- 基础实验_03_编码器：8位输入3位输出编码器-Experimental basis _03_ Encoder: 8 input 3 output encoder
33
- 基础实验_04_优先编码器 ：8位输入3位输出高位优先-Experimental basis _04_ priority encoder: 8 input 3 output high priority
44
- 基础实验_05_译码器 ：3位输入8位输出译码器-Experimental basis _05_ decoder: 3 input 8 output decoder
55
- 基础实验_06_优先译码器 ：优先译码器-Experimental basis _06_ priority decoder: Priority Decoder
shuzizhong
- vhdl数字钟通过fpeg仿真实现vhdl实验课设 -vhdl digital clock
FPGAVHDL
- vhdl例程代码大全，包含流水灯，数码管，AD,DA转换等-Guinness vhdl code routines, including water lights, digital, AD, DA conversion
FPGA-code--about-a-bookk
- 这是FPGA嵌入式项目开发一书的实例代码 对于FPGA初学者来说，一定的参考价值-it is code about FPGA, it is valuable for green hand!
AD5542
- DA芯片AD5542的驱动程序，已经完成调试-driver to AD5542
zhiliudy
- 基于VHDL语言的直流电压表的设计，可以实时显示电压数值，测量范围0~5V-DC voltmeter VHDL design language based, real-time display voltage value, measuring range 0 ~ 5V
baweiplj
- 基于VHDL语言的八位数字频率计设计，解决了以往例程逢9进1的错误，程序简单适合初学者-Based on VHDL eight digital frequency meter design, to solve routine every 9 into an error, the program simple for beginners
alu1
- 设计16位算术逻辑单元，能实现加、减、加1、减1、与、或、非、传送的功能。-Design of 16-bit arithmetic logic unit, to add, subtract, add 1, subtract 1, AND, OR, NOT, transfer function.
DDS_signal_genarator
- 这是一个利用verilog语言编写的信号发生器的例子，值得参考-this is a code about signal generator by VIERILOG LANGUAGE!