资源列表
UDP_receiver
- this is udp receiver application for sending packets through the ethernet
10BASET_RxD
- this is 10 base rxd application
10BASET_TxD
- this the code for the 10base txd application-this is the code for the 10base txd application
FIFO
- here is realized simple FIFO stack in vhdl. very simple example, but very helpful.
control
- 用VHDL语言编写的一个控制程序，主要功能是输入码同步，输出字和帧信号-VHDL language using a control program, the main function is to input code synchronization, and frame signals output word
write_reg
- 用VHDL语言编写的写存储器程序，可下载在FPGA中使用-VHDL language used to write memory program can be downloaded in the FPGA using
count
- 用VHDL编写的4、7、40、64、84计数器，可将程序中的具体数字设成任意值。-Using VHDL written 4,7,40,64,84 counter, you can program specific figures set to any value.
dianti
- 更多功能，有文件直接弄到MAX++里运行-Verilog vhdl
VHDLdianti
- 电梯控制 记忆，上升下降停站 超载报警故障.....。-Verilog EDA dianti
p_s
- 用VHDL语言编写的实现8位数据的并串转换，可下载在FPGA中-VHDL language with the realization of an 8-bit data, and the string conversion, can be downloaded in the FPGA in
LIBRARYIEE1
- 译码器，将八位输出转换为七段译码显示，相当于7448驱动译码管-Decoder, the 8 output is converted to seven segment decoding shows that the equivalent of 7448
VGAbasedonFPGA
- 基于FPGA的VGA彩条显示 可用PAXplusII仿真-FPGA-based VGA color display available PAXplusII Simulation of