资源列表
digital-clock
- 该数字钟论文是我用了一周的时间，采用Verilog DHL语言设计， Quratuse8.1仿真通过的文章-This paper is a digital clock I used a week, Verilog by DHL language design, Quratuse8.1 simulation through the article
first-follow
- first follow集合生成器 我晕。还嫌我说的少-first bu jiushi shang chuan dong xi ma
61EDA_C2293
- 《设计与验证Verilog程序》书中的全部代码，很全-" Verilog Design and Verification procedures" all the code book, it is full
spimaster
- 一般AD的spi配置代码，考虑的采样的时序问题。-General AD, spi configuration code, consider a sampling of the timing problems.
61EDA_C2345
- FPGA 开发与设计，适合新手开始对FPGA进行设计。希望有帮助-FPGA development and design, suitable for novice to begin FPGA design. Hope that helps
niosII
- 很好地描述了NOISII的串口、定时中断等各种实例-A good descr iption of the NOISII the serial port, timer interrupt, and other examples of
trunk
- hdl code for keypad scanner
VHDL
- VHDL的例程，详细讲解，在VHDL中使用层次设计（Cypress）-VHDL routines, detailed explanations, the use of the VHDL-level design (Cypress)
VHDL
- 此代码是用VHDL语言编写的一些小程序，可以运行学习之用-This code is written in VHDL small programs that can be used to run study
VHDL
- VHDL和数字电路设计课程实验指导，内容丰富-VHDL and digital circuit design course experiment guide, rich in content
cal
- 设计一个十进制计数器，由0到9进行循环计数，同时将计数结果通过数码管显示出来-Design of a decimal counter, from 0 to 9 for cycle counting, while counting resulted in the adoption of digital tube display
5
- 4*4矩阵状态机键盘 是数字电路设计中常用的信号输入法-4* 4 matrix keyboard state machine is commonly used in digital circuit design, signal input method