资源列表
Seven-Segment-LED
- 七段数码管按键识别，按下1键显示1，按下2键显示2-Seven-Segment LED identification keys, press the 1 key to show the 1, press 2 to display 2
38-decoder
- 38译码器，和一般的38译码器一样，二进制与十进制的对应-Decoder 38 and decoder 38 in general, as the corresponding binary and decimal
The-whole-point-of-time
- 整点报时with流水灯可调时分可调显示星期-The whole point of time with water lights around adjustable adjustable shows a week
clock
- FPGA的时钟算法 完整运行文件 通过Xilinx8.2的环境 波形仿真来实现时钟计数-FPGA clock algorithm to run it through a full environmental Xilinx8.2 simulation waveform to achieve the clock count
VHDL
- vhdl教程，很实用的，至少我认为对于我的课程设计有帮助-vhdl tutorial is very useful, at least I think that the curriculum design for my help
FPGAImageprocess
- 分析了传统电子稳像平台的缺陷,研究并设计了基于FPGA的专用平台。针对该平台研制过程中所涉及的一些关键问题进行了详尽的分析与探讨，给出了可行的解决办法。实验结果表明该平台工作稳定，扩展性好。-Reach and Implementation of Electronic Image Stabilization system based on FPGA
2138
- 步进电机驱动器两相细分步进电机 fpga+rom-Stepper motor drive sub-two-phase stepper motors fpga+ rom
vhdl
- 出租车计价器的vhdl语言描述，最新修改过的-Taximeter vhdl language descr iption of the latest revised
verilog
- 多功能数字时钟的verilog语言描述，基于quarters II平台-Multifunction digital clock verilog language descr iption of quarters II-based platforms
anjianxiaodou
- 基于verilog的按键消抖程序设计，包括整个工程文件-Based on the key consumer Buffeting verilog program design, including the entire project file
Flashcontrollerxilinx
- Single power supply operation — Full voltage range: 2.7 to 3.6 volt read, erase, and program operations — Separate VCCQ for 5 volt I/O tolerance n Automated Program and Erase — Page program: 512 + 16 bytes — Block erase: 8 K + 256 bytes
lariviere2008uclinux
- xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga