资源列表
FPGA_DDR_SDRAMverilog
- 基于Xilinx FPGA的DDRSDRAM的Verilog控制代码，使用的FPGA为Virtex-4，实现对DDRSDRAM的简单控制（对一系列地址的写入和读取）。-Xilinx FPGA-based DDRSDRAM the control of the Verilog code, the use of the FPGA for the Virtex-4, to achieve a simple DDRSDRAM control (on a series of addresses to wr
genode-fx-2009-03
- Genode FX is a composition of hardware and software components that enable the creation of fully fledged graphical user interfaces as system-on-chip solutions using commodity FPGAs.
SubDDS
- generate the sine wave using DSP Builder
T65_v302
- VHDL source codes of a 65xx compatible cpu core. Version 302.
fpga64_027
- VHDL source codes of the FPGA64, a fpga implementation of the C64 computer. Version for the c-one fpga board.
packer
- verilog data packer verilog data packer-verilog data packer verilog data packer verilog data packer
minimigJ_source_04_08_2008
- Verilog, c and asm source codes of the Minimig system, a fpga implementation of the Amiga computer. Version minimig-j used on the Minimig fpga board.
vending_machine
- 自动售货机模型，可以设置商品价钱及数量。0.5元及1元投币。可以返回最多1.5元。-Vending machine model, can set the price and quantity of goods. 0.5 yuan and 1 yuan coin. Can return a maximum of 1.5 per head.
VHDL06
- 16×4bit的FIFO设计代码，学习代码，请在下载24小时后删除。-16 × 4bit the FIFO design code, learning the code, please delete after 24 hours to download.
music
- 基于FPGA的乐曲发生器设计，以 EDA 技术为核心的能在可编程 ASIC 上进行系统芯片集成的新设计方法-FPGA-based music generator designed to EDA technology as the core of the ASIC can be carried out in a programmable system-on-chip integration of the new design method
VHDL05
- ALU算术逻辑运算模块设计代码。内容简单。是个不错的代码，学习的人可以下载参阅。-ALU arithmetic logic operations module design code. Simple. Is not a bad code, people can download the study refer to.
VHDL04
- 4位微处理器系统的顶层描述代码，本人亲自测试，代码很简单。明了。内容无毒。放心下载使用-4 top-level descr iption of the microprocessor system code, I personally tested the code is very simple. Clear. The content of non-toxic. Download ease the use of