资源列表
VHDL03
- 全加器仿真程序代码，本人亲自测试，代码简单，安全无毒。放心下载和使用。-Full adder simulation code, I personally tested the code simple, safe non-toxic. Ease to download and use.
VHDL02
- 加法器和全加器参考程序，由VHDL代码编写。初学者可以看一看。内容无毒，下载请杀毒使用。-Adder reference procedures, prepared by the VHDL code. Beginners can take a look at. Content-free, download antivirus, please use.
VHDL01
- 全加器仿真程序. 大家可以参考下 ，本人检查无误。无毒。如有问题，请来信咨询。-Full adder simulation program. You can refer to, I check the accuracy. Non-toxic. If you have any questions, please contact us advice.
ISE_tutorial_verilog
- Xilinx ISE Tutorial For helping HOW TO
20081129464173846
- 介绍Verilog HDL, 内容包括： – Verilog应用 – Verilog语言的构成元素 – 结构级描述及仿真 – 行为级描述及仿真 – 延时的特点及说明 – 介绍Verilog testbench • 激励和控制和描述 • 结果的产生及验证 – 任务task及函数function – 用户定义的基本单元(primitive) – 可综合的Verilog描述风格-Introduced the Verilog HDL, in
512Mb_ddr_Modules
- DDR and DDR DIMM Controller
Interfacing_to_External_Static_Ram
- Interfacing to External Static Ram This module colntroller is for srams
uart_txd
- 基于verilog hdl的UART串口发送子程序。-Verilog hdl a UART-based serial port to send subroutine.
uart_rxd
- 基于verilog hdl的UART串口接收子程序。-Verilog hdl a UART-based serial port to receive subroutine.
shiftbetweenserializationandparallel
- 在数据的输入过程中可完成并行数据和串行数据的转换-shiftnbetween berialization and parallel
usart
- Usart model in vhdl code
MediaMobile
- moving average vhdl source code