资源列表
eleclock
- VHDL实现的电子钟的基本功能，带QUARTUE工程文件-VHDL realization of the basic functions of electronic bell with engineering documents QUARTUE
Device
- A VHDL program to simulate the behaviour of a device,
TestMachine
- VHDL source code for test machine.
EP1C3_12_1_2_MOTO
- 基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写，压缩包里是Quartus下的工程。-FPGA-based PWM DC motor control and stepper motor-driven control of a breakdown. The use of VHDL language, compression bag is under the Quartus project.
EP1C3_12_3_VGA
- 基于FPGA的VGA彩条显示程序，共开发VGA的朋友参考。没有采用DA，因此只有8中颜色（输出直接连到VGA的RGB）。其中行、场同步部分用计数器完成。程序用VHDL编写。-FPGA-based VGA color display, with a total development of the reference VGA friends. Did not use DA, only 8 colors (directly connected to the VGA output of the RGB
VHDL
- vhdl语言详解，入门必看。建议初学者仔细阅读-no
dianzishejishili
- 电子系统设计实例 设计语言VHDL 实验仪器 杭州康芯gw48eda 开发系统-Examples of electronic system design languages VHDL core experimental apparatus gw48eda Hangzhou Culture Development System
mul4
- 分析二进制乘法中计算步骤（多少次加法，何时进行），实现一个有限状态机，执行乘法运算。-Analysis of binary multiplication in the calculation of step (adding the number of times, when it will be), the realization of a finite state machine, the implementation of multiplication.
p2s
- 并串转换器：将并行输入的信号以串行方式输出，这里要注意需先对时钟进行分频，用得到的低频信号控制时序，有利于观察结果（可以通过L灯观察结果）-And series converter: the input signal in parallel to serial output, where attention should be paid to the need to carry out first clock frequency, low-frequency signals received b
counter
- 利用EDA工具MAX-PlusII的VDHL输入法，输入VHDL程序，实现2位计数器，在七段译码器上以十进制显示：0、1、2、3、0、...。时钟信号使用83管脚。采用自动机状态转换方式设计该计数器；建立相应仿真波形文件，并进行波形仿真；分析设计电路的正确性。-The use of EDA tools VDHL of the MAX-PlusII input method, enter the VHDL program, the realization of two counters, in t
voter
- 用VHDL语言设计三人表决器 新建VHDL设计文件并保存 检查编译 波形仿真 -Design using VHDL language VHDL three new voting system for the design document and save it to check the compiler waveform simulation
addDisplay
- 四人抢答器，用quartus编译过的，vhdl语言，说明详细，欢迎各位下载，-add display led