资源列表
UART_DMA
- 基于ALTERA公司的NIOSII的串口通信DMA传输设计-NIOSII based on ALTERA s DMA transfer of the serial communication design
IIC_bus
- 基于ALTERA公司的NIOSII的I2C总线传输应用设计-NIOSII based on ALTERA s application of the I2C bus transmission design
GPS
- 基于ALTERA公司的NIOSII的GPS信息接收系统的设计-ALTERA company NIOSII based on the GPS receiver system design information
PAIRCRASH
- 基于ALTERA公司的NIOSII的对对碰游戏的设计-NIOSII based on ALTERA s right right touch of the game design
Application_of_pseudo_random_sequence_verilog_desi
- 伪随机序列应用verilog设计.rar-Application of pseudo-random sequence verilog design.rar
Galois_field_multiplier_verilog_design
- 伽罗华域GF（q）乘法器verilog设计.rar-Galois field GF (q) multiplier verilog design.rar
Common_adder_verilog_design
- 上传文件为：常用加法器verilog设计.rar-Upload files as follows: common adder verilog design. Rar
Common_multiplier_verilog_design
- 上传文件为：常用乘法器verilog设计.rar-Upload files as follows: common multiplier verilog design. Rar
CORDIC_design_verilog_digital_computer
- CORDIC数字计算机verilog设计.rar-CORDIC design verilog digital computer. Rar
11114
- 秒表功能的显示 LCD1602显示,自动加1 VHDL -SECOND WATCH 测试通过
xapp610
- Verilog code for 2D-DCT with detailed documentation.
clock
- 这是一个电子时钟的VHDL语言程序，非常好，注释也比较清晰，它包括电子时钟的所有功能。-This is an electronic clock VHDL language program, very good, the Notes are also clear, which includes all the features of the electronic clock.