资源列表
iic
- 一个verilog源代码，可用ISE等实现，功能为I2C接口标准建模。-A verilog source code, can be used, such as the realization of ISE, the functional model for the I2C interface standard.
FPGA
- 基于FPGA的数字频率计的设计11利用VHDL 硬件描述语言设计,并在EDA(电子设计自动化) 工具的帮助下,用大规模可编程逻辑器件(FPGA/ CPLD) 实现数字频率计的设计原理及相关程序-FPGA-based design of digital frequency meter 11, the use of VHDL hardware descr iption language design, and EDA (electronic design automation) tools with
DS18b20
- 这是一个工业用的普通温度传感器DS18b20的VHDL文件，直接可用，可为FPGA的其他逻辑模块或者Nios提供接口，其输出为18b20的11位温度暂存器的值。-This is a common logic module for DS18b20 which can provides parallel outputs for Nios II or other internal units of FPGA.
l_standard_1c6
- RT8019网络控制器在FPGA中的驱动设计-RT8019 network controller in the FPGA design of the drive
multiplier
- 乘法器在FPGA中的VHDL代码实现教程-Multipliers in the FPGA code in VHDL Tutorial
FIR
- FIR在FPGA中的VHDL代码实现教程-FIR in FPGA code in VHDL Tutorial
decoder
- 一个verilog源代码，用于译码器的编程。-A verilog source code, for programming decoder.
counter16
- 一个verilog源代码，作用是计数器的建模。-A verilog source code, the role of the counter model.
RAM
- 这是个双端口双端口ram的定义，当然读者在此基础上还可以扩充-This is a dual-port dual-port ram definition, of course, on the basis of the readers can also be expanded
mux4
- 这是个四输入乘法器，还可以进步扩充端口-This is a four-input multiplier, but also the progress of the expansion of port
aianxiaodou
- 用vhdl语言实现对按键的消抖，消除按键的抖动对系统造成的误判-Vhdl language used to achieve the elimination of key Buffeting to eliminate jitter button on the system caused by misjudgment
anjian
- 最基本的vhdl程序，能实现一小时的计时，且加入按键功能-Vhdl basic procedures, to achieve a one-hour time, and by adding key features