资源列表
BusDelay
- buffer delay vhdl model
adder
- verilog 加法器设计 在modelsim下方针-verilog adder
elevator
- 用VHDL编写的一个电梯控制程序，花了很长时间，应该很不错的-VHDL prepared with a elevator control procedures, took a long time, should be very good
clock
- Clock based on the VHDL design language, the revised time alarm can be set up
sever_communicaton
- 串口通信程序，对初学单片机的人很有用的。看看a-Serial communication program for beginner who SCM useful. Take a look at a
maoci
- 用VHDL编的一个程序，用来控制时钟信号的频率-Using VHDL for a procedure, used to control the frequency of the clock signal
Wireless_capture
- 很多仪器都输出同步时钟，这是一个区毛刺的程序。编得很巧妙！-Many instruments are output synchronous clock, which is a district procedure burr. For very clever!
DM642_syn
- 一个用vHDL语言编的同步程序，对图像处理人员有帮助哦-VHDL language used for a synchronization process, the image processing staff helpful Oh
holidaywork
- 机器状态机。控制工作方式。用vhdl写的。很不错哦-Machine state machine. Control work. Written by vhdl. Oh well
adder44
- adder 4 + 4 bits, for use with a Altera, and 2 displays 7 segments-adder 4+ 4 bits, for use with a Altera, and 2 displays 7 segments
AVR_UARTFPGA
- 基于VHDL（verilog）语言的UART的设计与实现。全面模仿AVR的UART功能，与AVR直接实现接口调试。资料全面完整。-Based on VHDL (verilog) Language Design and Implementation of UART. UART fully mimic the function of AVR, and AVR debugging interface directly to achieve. Overall integrity of the infor
sun1602
- 能驱动LCD1602的VHDL程序，芯片是ACTEL的Fusion系列-Vhdl LCD1602 for ACTEL