资源列表
BJ-EPM_entire_board_test_code.
- BJ-EPM240V2实验例程以及说明文档实验之BJ-EPM整板测试用代码,BJ-EPM240V2 experimental test routines as well as documentation of the entire board BJ-EPM test code
Verilog-vga
- 基于Verilog的VGA显示汉字、字符的例子以及vga资料-Verilog' s VGA display Chinese characters based on the character of the examples and information vga
SLAVE-FIFO16-test
- 基于FPGA的USB调试代码，包括上位机代码、驱动程序、应用程序、下位机代码。-USB debugging code based on FPGA, including PC code, driver and PC, application code.
DS18B20_NEW2
- DS18B20 FPGA 数字温度计-DS18B20 FPGA digital temperature
VGA
- vrilog写的VGA显示程序。 只是普通的程序，-vrilog write VGA display program.
core_arm_latest.tar
- ARM core for FPGA in VHDL Language
usb_test1
- usb slaver fifo写程序，将产生的临时数据传送到slaver fifo-usb slaver fifo write programs, will produce temporary data transfer to the slaver fifo
LCD
- LCD 16x2 Driver with UCF static text
avs_aes_latest
- This is source code for something very important that is AVS AES standard hardware code for implementation both ASIC and FPGA
rom_255
- 入通过键盘控制或者通过50MHz晶振分频后以每1秒步长发生变化，通过8位并口输出数字信号，并将该数字信号经过译码电路后用七段数码管提示输出信息。-By controlling the keyboard or by 50MHz crystal occur long after the division to change every second step, through the 8-bit parallel digital output signal, and the digital sign
fir_verilog_matlab
- 本设计是基于FPGA的一个FIR低通滤波器设计，要求使用Verilog语言编写滤波器模块，通过编译和综合，并通过Matlab和modelsim联合仿真验证设计结果。-This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design re
DSP_design_based_on_FPGA
- 用FPGA设计DSP,2007年上海FPGA高级研修班清华博士贺光辉讲义-FPGA Design with DSP, 2007 in Shanghai FPGA advanced training classes Tsinghua notes Dr. He Guanghui