资源列表
miaobiao
- 使用VHDL\FPGA实现秒表的设计，包含所有源码。-Use VHDL\FPGA to achieve a stopwatch
quanjiaqi-verilog
- 基于verilog语言的编写的全加器，基于verilog语言的编写的全加器-quanjiaqi
FinalLCD
- VHDL for LCD interfacing with Spartan 3E FPGA board
keypar_4_4
- interfacing 4*4 matrix keypad with VHDL code
counter
- 4 bit up counter using VHDL code
bitcounter
- one bit up counter using VHDL code -one bit up counter using VHDL code
DFF
- D flip-flpo design using VHDL codes
zhitouzi
- 原创。掷骰子游戏，VHDL，quartus，北京邮电大学数电实验，实现随机掷骰子游戏，在数码管显示点数，点阵显示输赢，有开机动画以及开机音乐，可实现多人游戏等-games, VHDL, quartus,experiments of BUPT, pure originality,random game, in the digital display dots, dot matrix display winning or losing, there are boot animation and bo
VerilogHDL-entry-of-a-study-books
- VerilogHDL 入门必看书籍，通俗易懂的语言使初学者对建模有一个更直观的印象。-Getting VerilogHDL must-see books, in plain language so that beginners modeling a more intuitive impression.
xc6slx9_dnareader_12.4
- 读和验证Xilinx的DeviceDNA值，用于系统加密-Read and verify Xilinx Spartan6 DeviceDNA
3_05_SPI_Wr_Rd
- SPI读写实验，verilog源码，编译通过，有需要的拿去用-SPI source code
6_14_SOC_SD
- SD驱动，xilinx microblaze源码，编译通过，有需要的拿去用-SD source code