CDN加速镜像 | 设为首页 | 加入收藏夹
当前位置: 首页 源码下载 嵌入式/单片机编程

资源列表

« 1 2 ... .48 .49 .50 .51 .52 5853.54 .55 .56 .57 .58 ... 33646 »
  1. SPI_Master

    0下载:
  2. 在FPGA中此源代码可作为SPI的主机传输代码,如有分开用的时候,此源代码会很方便,简单易懂-This source code in an FPGA can be used as SPI host transmission code, if separated by time, this source will be very convenient, easy to understand
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-16
    • 文件大小:3.65mb
    • 提供者:田勇
  1. 64KAIGUAN

    0下载:
  2. 此代码是一分64路开关,通过串口控制具体开关的关断,简单,清晰-This code is a sub 64-way switch, via the serial control switch off specific, simple, clear
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-30
    • 文件大小:11.4mb
    • 提供者:田勇
  1. 7duanshumaguan

    0下载:
  2. 7段数码管,显示计数器计数的个数,源代码简单,清晰-7-segment display counter counts the number of source code is simple, clear
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-12
    • 文件大小:1008byte
    • 提供者:田勇
  1. uart-verilog

    0下载:
  2. 经典rs232串口Verilog源代码,晶振可随意根据具体情况更改,代码风格非常清晰,明了!-Classic rs232 serial Verilog source code, the crystal can be altered depending on the circumstances, the code style is very clear, clear!
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-13
    • 文件大小:1.51kb
    • 提供者:田勇
  1. flappybird

    0下载:
  2. 这是我练手时写的一个小游戏,是基于flappybird游戏原理制作的,用硬件完成其功能。主要用Verilog语言完成功能描述,通过ps2键盘的空格键控制飞翔,在VGA上进行显示。本工程已在basys2实验开发板上进行验证,画面略显粗糙,见谅。-This is what I wrote when practiced hand of a little game, is based on the principle of making flappybird game, with the hardwar
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-11
    • 文件大小:2.16mb
    • 提供者:wei
  1. i2c_ms5611

    0下载:
  2. FPGA实现 I2C 总线读取MS5611气压计的程序-FPGA implementation of the I2C bus to read the MS5611 barometer
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-14
    • 文件大小:3.5kb
    • 提供者:yxs
  1. vip_ex9

    0下载:
  2. 本段源码实现功能为从摄像头采集到VGA输出的FPGA代码,内附编译好的工程文件-This segment functions as a collection source implementation the camera to the VGA output of the FPGA code, containing compiled project file
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-06-17
    • 文件大小:24.93mb
    • 提供者:
  1. h264

    0下载:
  2. This is an example top level module for the H264 submodules. Each implementation will differ at the top level due to differing number of video streams, resolution, and RAM type and interface. This is thus just a skeleton implementation.- T
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-29
    • 文件大小:51.91kb
    • 提供者:aa
  1. vga_lcd

    0下载:
  2. VGA LCD interface Uses gray codes to move one clock domain to the other. Flags are synchronous to the related clock domain - empty: synchronous to read_clock - full : synchronous to write_clock-VGA LCD interface Uses gray codes to
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-29
    • 文件大小:45.7kb
    • 提供者:aa
  1. e1-framer

    0下载:
  2. e1 framer / de-framer based on itu-t standards state machine using GRAY CODE (or trying to use GRAY CODE
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-14
    • 文件大小:2.52kb
    • 提供者:aa
  1. ddr_sdr

    0下载:
  2. DDR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted to any other DDR SDRAM device-DDR SDRAM Controller Core - has been designe
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-29
    • 文件大小:36.88kb
    • 提供者:aa
  1. jpeg-coder

    0下载:
  2. EV_JPEG_ENC core is intended to encode raw bitmap images into JPEG compliant coded bit stream. JPEG baseline encoding method is used.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-29
    • 文件大小:59.24kb
    • 提供者:aa
« 1 2 ... .48 .49 .50 .51 .52 5853.54 .55 .56 .57 .58 ... 33646 »
搜珍网 www.dssz.com