资源列表
PCI_arbi
- PCI总线仲裁参考设计Verilog代码。最大支持6个master的仲裁。-PCI bus arbitration reference design Verilog code. Maximum six master arbitration.
eetop[1].cn_axibusregslice
- axi总线读写通道插入一级寄存器模块verilog源码,已验证- a slave interface is simple to achieve, need to look at
DW8051_ALL
- DW8051Verilog源码实现 含有说明书 绝对可用-DW8051Verilog source to achieve contain instructions absolutely available
fir_anthor405
- 基于DSP Builder在simulink开发环境下利用fir_compiler搭建fir滤波器，有很好的借鉴作用-Based on the DSP Builder and simulink development environment,by using fir_compiler build a fir filter, it can be a good reference
cap_data_model
- Linguagem em VHDL - Capt_data
digitalclock
- Digital clock 8 segments
hamming
- Códigos Hamming cod 7-3
REQUEST
- Request - Para Sensores
Sensor
- Sensor de Temperatura
Lightflu_cycle
- 使用verilog编程实现流水灯的控制程序实现8位灯的循环流水亮灯-Verilog programming control procedures of the light water recirculating eight lights lit
VHDL_uart
- 用xilinx的FPGA-spartan3E实现uart，固定波特率9600，偶校验，系统时钟50MHz，能够实现将从串口调试助手发送到FPGA的数据重新发回串口调试助手-using xilinx s FPGA-spartan3E to implement uart with a baudrate of 9600, even parity check. The system frequency is 50MHz.It can turn the data from serial assistant
elevator-verilog-code
- SRAM CONTROLLER CAN GIVE YOU CORRET IDEA ABOUT VERILOG