资源列表
DesignofEquivalentSampleStorag
- 一些关于示波器的论文， 基于FPGA的等效采样存储示波器设计,A number of papers on the oscilloscope, DesignofEquivalentSampleStorageOscilloscopeBasedonFPGA
gh_vhdl_lib_v3_48.rar
- The GH VHDL Standard Parts Library is a collection of basic VHDL parts that may be included in larger designs. There is nothing wrong with modifying library parts so that they will meet the system requirements.,The GH VHDL Standard Parts Library is
DE2_LCM_TV_PAL.zip
- DE2上的基于FPGA视频开发资料第3部分！！！,DE2 video
DE2_LCM_TV_Simple.zip
- DE2上的基于FPGA视频开发资料第4部分！！！,DE2 video
qfq.rar
- 移位相加乘法器设计。附有工程实例及ppt说明。,Add multiplier design shift. Ppt with example and descr iption.
bono_evb_cpld_1.2.rar
- sources of CPLD (fpga) from freescale i.MX27 Avanced Designe System Develpment Kit board,sources of CPLD (fpga) from freescale i.MX27 Avanced Designe System Develpment Kit board
CODE.rar
- AHB总线下的slave ram的verilog代码,AHB bus slave ram verilog
脉宽测量程序源代码
- 脉宽测量：可以用来测量脉冲宽度，周期技术信号显示从00到FF，共16x16位,Pulse width measurement: can be used to measure pulse width, cycle technology signals from 00 to FF, a total of 16x16-bit
cy7c1371c_vhdl_10.zip
- cy7c1371c ZBT SRAM 的仿真模型，VHDL编写。,the simulate model of cy7c1371c,VHDL language.
IS-95/CDMA2000基带成形滤波器的实现
- IS-95/CDMA2000基带成形滤波器的实现 IS-95滤波器的实现： 本次设计采用转置型结构，并用展开技术将字串行架构转换成字并行处理架构，从而提高运行的速度。本次设计中采用展开因子J=4的展开转换技术。设输入数据为filter_in，输出数据为filter_out，则其展开因子J=4的并行处理系统如下图所示 ,IS-95/CDMA2000 base-band filter shaping to achieve IS-95 filter to achieve: the desig
scramble.rar
- 通信用加扰码VHDL电路，解决光传输过程中的连零和连一码的出现。,Communication scrambling circuit VHDL Code
8B-10B.rar
- 一种新的8B-10B编解码硬件设计方法，希望对您的工作有所帮助。,A new codec 8B-10B hardware design, and I hope to be helpful to your work.