资源列表
5
- vhdl的仿真 quartus 2的flv视频 -VHDL simulation of the flv video quartus 2
complex
- 时钟，信号灯verilog for FPGA
GPS去载波verilog实现
- 该源码用verilog实现gps信号的去载波过程
seg7
- verilog HDL编写的FPGA定时器并用数码管显示(Verilog HDL prepared by the FPGA timer and digital display)
chuankou
- UART loopback测试实例，接收PC端发送的UART数据，原数据返回给PC端，即loopback功能 可用FPGA开发板验证(The UART loopback test example receives the UART data sent by the PC terminal, and the original data is returned to the PC terminal, that is, the loopback function.)
verilogsourcecode
- 提供了verlog完整工程文件、设计源文件和说明文件-Provides a verlog complete project file, design source files and documentation
Vertical-Handover-between-WiFi-and-UMTS-Networks-
- Vertical Handover between WiFi and UMTS Networks
ddstest
- 这是一个电子设计dds设计的项目，本设计居于FPGA的dds，该设计舍弃了单片机作为控制的思路，在fgga中嵌入NIOSII来作为控制，界面采用12864，但是菜单页面丰富，采用菜单结构编辑了多层次的界面，整个系统看上去很简洁，希望对搞电子设计的有帮忙，本人也是搞电子设计有一段时间。-dds which base on niosII and fpga
Test_LED[1]
- 用VHDL实现的一个工程，可以参考来学习FPGA的设计-VHDL achieved with a project, you can reference to learn the design of FPGA
ddr2_sdram_latest.tar
- 1.初始化-Sequenz的RAM 2. Automaic写Sequenz（写入16数据字每一个64位的RAM） 3.自动读Sequenz（从RAM读出的第一个数据字）-1. Init-Sequenz for the RAM 2. Automaic Write-Sequenz (writes 16 Datawords each 64Bit to the RAM) 3. Automatic Read-Sequenz (reads the first Dataword the
Aword解密软件
- 绿色在线破解WORD加密功能，经过多次使用功能正常可用。(Green online cracking WORD encryption function, after repeated use of normal function available.)
FPGA_USB
- 自己写的用于测试USB和FPGA通信的程序，主要是通过USB发送数据，来测试FPAG的LED跑马灯-Write for testing USB and FPGA communication process, mainly through the USB to send data to test the LED Marquee FPAG