资源列表
verilogsram
- 基于IS62LV256-70U存储芯片为例，对SRAM进行读写操作，加深对存储芯片的时序图的理解。-Based IS62LV256-70U memory chips, for example, the SRAM read and write operations, the timing diagram deepen the understanding of memory chip.
ex1_config_as_jtag
- FPGA器件有三类配置下载方式：主动配置方式（AS） 、被动配置方式（PS）和最常用的基于JTAG的配置方式。 本代码对AS和JTAG的配置方式进行了研究。-FPGA devices have three types of configuration download: active configuration (AS), passive configuration (PS) and the most common way of JTAG-based configuration. The cod
uartfifo
- 该实验主要实现一个串口发送器功能， 该发送器的数据是从FIFO中读取的。也就是说，只要FIFO中有数据，串口发送器就会启动，将数据发送出去。 -The main experimental realization of a serial transmitter function, which sends the data is read the FIFO. In other words, as long as there is data in the FIFO, serial transmitt
vga256
- 基于SF-EP1C开发板的256色VGA显示实验，VGA显示是FPGA中重要的一部分，此代码进行了初步研究。-SF-EP1C development board based on a 256-color VGA display experiment, VGA display is an important part of the FPGA, this code has been studied.
FPGA_vga_char
- FPGA的学习中，VGA字符显示是非常重要的，这段代码对VGA的字符显示进行了初步研究。-FPGA learning, VGA character display is very important, this code to display VGA characters were studied.
ex9_cof_M4K_test1
- FPGA器件中通常嵌入一些用户可配置的存储块，此代码是关于基M4K块的单RAM配置仿真实验。 -FPGA devices are usually embedded memory blocks some user-configurable, this code is based on a single M4K block RAM configuration simulation.
my_example
- 基于SOPC构建的CPU，用DE2-70做的LCD显示，用c语言进行编写。-Based on SOPC built CPU, LCD display with DE2-70 do with the c language written.
SOPC_LCD
- 基于SOPC构建的CPU，用DE2-70做的LCD显示，用c语言进行编写。-Based on SOPC built CPU, LCD display with DE2-70 do with the c language written.
6luqiangda
- 六路抢答器，保证抢答模块绝对一输出，无后门。-All the buzzer, an absolute guarantee that vies to answer first module output, no back door.
uart
- 利用xilinx 公司的ise软件基于verilog HDL实现UART控制程序-based on the xilinx ise and use verilog HDL language to achieve the purposes that control the uart.
led_111
- 利用xilinx公司的basys2实验班实现流水灯程序-Use xilinx s basys2 experimental class program to achieve water lights
time
- 利用quatars,vhdl实现有倒计时功能计时器，设计定时器功能有正向计时和倒向计时，可暂停计数，继续计数。当倒向计时计数为0时会报警（时间为1分钟）在报警期间可以认为关闭-Using quataus, VHDL realization which has the function of the countdown counter, timer design features are timing and backward timing, can suspend count, continue