资源列表
CIC_filter
- 三级级联梳状滤波器（CIC）的verilog实现。顶层模块top_moduole下面包含三个子模块，积分模块integrated，抽取模块decimate和梳状滤波器模块comb，已验证可综合通过并实现CIC功能-Three-level cascade comb filter (CIC) verilog implementation.Top-level module top_moduole below contains three child module, integral module in
case-and-if-programing-in-verilog
- Case语句和if语句在电路设计中的注意事项，各种产生锁存器的原因分析，以及原代码-case and if using in verilog
cnt5_fsm
- 这是一个简单的vhdl状态机例程，适合新手学习，简单易懂。-This is a simple state machine vhdl routines, suitable for beginners to learn, easy to understand.
DFF12
- 简单modelsim testbench测试工程，包含源码和testbench文件-Modelsim testbench simple test project, including source code and testbench files
uart_tx
- 带有奇偶校验功能的的串口发送模块，实现uart功能。verilog硬件描述语言实现-With the function of parity of serial port to send module, uart functions.Verilog hardware descr iption language to realize
init_LCD
- Initializes Toppoly TD043MTEA1 LCD. R02: Type 1 Dot inversion, VD and HD low polarity, Latch data on falling edge, 800x480RGB R03: Software register standby, pre-charge enabled, 100 drive capacity, PWM enabled, VGL pump enabled, cp_clk enabled, n
qsys2014
- 介绍qsys的使用，是基于quartus13.0版本的操作，比较好的一本教程-Introduced the use of qsys, is a version of the quartus13.0 based operation, a good tutorial
GPS
- 本程序实现功能为接受GPS接收机时间信息，并编码形成IRIG-B时间码，同时跟设备总线通过485进行通信。包括原理图，单片机程序及CPLD程序。-This program implements functionality GPS receiver for receiving the time information, and encoding IRIG-B time code is formed, while with the device 485 to communicate via the
DDS
- 基于DDS的信号发生器，产生10KHZ-15KH的正弦波、三角波信号；频率字M按键输入，每次增量1；-DDS-based signal generator
sdram_basemod
- 可以实现sdram的页读写功能，其中加了两个FIFO缓冲器，只需稍改就可以加入工程。-Sdram page can read and write capabilities, including the addition of two FIFO buffers, just a little change can join the project.
ADC_TLC549
- verilog编写，利用fpga自带ADC芯片tlc549实时采集电压信号，并通过数码管显示。-verilog write, use fpga comes tlc549 ADC chip voltage signal real-time acquisition and through digital display.
rx_tx_demo
- 用verilog实现的少量字符串的连续收发，添加了FIFO模块，稍微修改下就可以使用。-Receive a small amount of a continuous string of verilog implementation, added FIFO module, can be used under slightly modified.