资源列表
cordic
- cordic的代码，适合初学者学习和交流-cordic code, suitable for beginners to learn and exchange
FFT16
- FFT变换的代码，适合初学者学习。16点FFT-FFT transform code, suitable for beginners to learn. 16 FFT
Infrared-light-transmission-
- 将音频信号输入到电路中，发射端利用红外光发射出去，接收端进行接受，经AD处理，由声音的高低控制灯的量灭，另外将温度实时采集并显示在数码管上，详情请见压缩包中的文档-Audio signal input to the circuit, transmitter with infrared emission, the receiver to accept the AD processing, controlled by the sound of the amount of light, in addi
demo4
- AXI4-stream协议，用于调试，测试代码，IPcore-The AXI4-stream protocol, used to debug, test code, IPcore
SUBWAY
- ① 设计一个符合武汉市现行计价标准的地铁自动售票机。②每个地铁站设置一个开关，设置“10元”和“1元”两个投币口（用开关模拟），设置四个数码管，分别显示投币金额和找零金额，用指示灯表示出票。每次操作限购1张票。 -1、Designing a valuation in line with the current standard of Wuhan Metro ticket vending machines。2、Each subway station setting a switch, set
gdi1
- Viterbi decoder is used for decoding data encoded using Convolution Forward Error Correction codes or data that suffers inter-symbol interference. They occur in a large proportion of digital transmission. Viterbi decoders employed in digital wire
QAM_verilog
- 基于FPGA的16QAM，用verilog编写，其中DDS为自己编写，含设计文件和testbench。已通过moldesim软件仿真。 -FPGA-based 16QAM, with verilog writing, including DDS for their preparation, including design files and testbench. Simulation software has been through moldesim.
proyecto-I2C
- It s a VERILOG code to initiate a I2C protocol on an FPGA and an EEPROM of 512 KB
dds_cordic
- 这是我自己编的一个基于流水线结构CORDIC算法实现DDS，32位的频率控制字的输入，CORDIC算法的迭代次数为15次。-This is my own DDS based on series of the pipelined CORDIC algorithm， a frequency control word：32 bit .The number of CORDIC iterations for the 15 time。
TLC1650
- TLC1650驱动程序 Verilog HDL-TLC1650driver Verilog HDL
ML605_RX_H264
- H.264视频压缩硬件语言，基于ＦＰＧＡ的设计语言。非常棒的语言设计-Solution of H.264 video compression hardware design language, based on FPGA language
dianzhen
- 基于FPGA的点阵模块，输入汉字信息后可以逐行扫描-After the dot-based FPGA module, input Chinese information can be progressive scan