资源列表
traffic_control
- traffic controller verilog source code 1
traffic_control_tb
- traffic controller verilog test bench code 2
vsim
- flii adder wave form 3
laser_timer
- laser timer source and test bench code 4
fulladdr
- full adder source and test bench 5
Digital-clock
- 设计一个数字钟，使用vhdl语言进行编写，以上是源程序-The design of a digital clock, using VHDL language, the above is the source
D_flipflop
- D flip flop source and test bench verilog code 6
fft-ip-core
- 通过调用ISE中的fft IPcore实现了fft计算，输入数据通过textio从文本文件读入，处理后的数据再读入文本中。由于数据精度问题，与MATLAB计算的结果存在一定的误差-By calling the ISE of FFT IPcore implements the FFT computation, the input data through textio read a text file, after processing the data to read the text aga
zong
- 基于FPGA的频率计设计：通过不同的按键设置，可检查0.01-100M不同频段的频率，并通过数码管显示-FPGA design is based on the frequency meter: different set of keys, you can check 0.01-100M different frequencies bands, and through a digital display
SPIcontroler
- spi控制器，crc模块，top模块，crc测试模块，数据传输测试模块-spi controler
uartverilog111
- 实现FPGA与Pc无线蓝牙交互，可移植，编译通过-Implement FPGA and Pc Bluetooth interactive, portable, compiled by
Traffic-light
- 基于vhdl语言的交通信号灯控制程序，使用软件为Quartus II，硬件为FPGA。-Traffic lights control procedures