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  1. DDRSDRAM

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  2. 用vdhl编写的DDR sdram控制器,采用模块化编写,条理清楚,注解详细,附有存储器的说明。-the ddr sdram controller base vhdl
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-06
    • 文件大小:464.56kb
    • 提供者:tangjieling
  1. verilog_tutorial

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  2. Chapter 1 Introduction Chapter 2 History of Verilog Chapter 3 Design and Tool Flow Chapter 4 My First Program in Verilog Chapter 5 Verilog HDL Syntax and Semantics Chapter 6 Gate Level Modeling Chapter 7 User Defined Primitives Chapter
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-27
    • 文件大小:755.11kb
    • 提供者:zhangyung
  1. VHDL_Programming_by_Example

    0下载:
  2. Copyright © 2002 by The McGraw-Hill Companies, Inc. All rights reserved. Manufactured in the United States of America. Except as permitted under the United States Copyright Act of 1976, no part of this publication may be reproduced or distribut
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-07
    • 文件大小:1.78mb
    • 提供者:zhangyung
  1. Design_of_Embedded_Control_Systems

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  2. This volume presents new results in the design of embedded control systems, each chapter authored by an expert. The text focuses on current issues with new approaches for the analysis and synthesis of discrete systems and is aimed at programmable log
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-08
    • 文件大小:1.9mb
    • 提供者:zhangyung
  1. Embedded_Design_Programming

    0下载:
  2. This book combines Simulink for high level programming and SystemC for the low level software development. This approach is illustrated with multiple examples of application software and MPSoC architectures that can be used for deep understanding of
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-12
    • 文件大小:2.83mb
    • 提供者:zhangyung
  1. vga_demo2

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  2. VGA controller : Genarate a VGA signal from your inout information as color info of each pixel-VGA controller : Genarate a VGA signal from your inout information as color info of each pixel
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-05
    • 文件大小:544.69kb
    • 提供者:iman
  1. EDAplvj

    0下载:
  2. 4挡频率及设计 用于测量制定信号的频率 Verilog语言编写-4 block design used to measure the frequency and the frequency of the signal developed Verilog language
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-17
    • 文件大小:409.73kb
    • 提供者:沈小响
  1. chfqi

    0下载:
  2. 简易5位乘法器的设计 用于EDA课程设计和VHDL的入门学习-Easy 5 Multiplier for EDA VHDL introduction to course design and learning
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-09
    • 文件大小:731.47kb
    • 提供者:沈小响
  1. subtracter_4

    0下载:
  2. 好还是verilog,现在你记忆可以,是关于FPGA的设计-Good or verilog, now you can remember, is the design on the FPGA
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-04
    • 文件大小:97.91kb
    • 提供者:杨希
  1. MaxPlus2_novice_learning_manuals

    0下载:
  2. MaxPlus2新手学习手册:学习软件的必备教程,很详细!-MaxPlus2 novice learning handbook: the essential learning software tutorial, very detailed!
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-17
    • 文件大小:230.16kb
    • 提供者:io
  1. CIC

    0下载:
  2. 五阶CIC滤波器,用于降低数据传输速率。数字下变频技术不仅是软件无线电核心技术之一,还是中频数字化接收系统重要组成部分。数字下变频技术中广泛用到级联积分梳状滤波器(CIC滤波器)-CIC filter
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-09
    • 文件大小:1.36mb
    • 提供者:姚琼琼
  1. counter

    0下载:
  2. 一个倒数计时的模块,以秒为单位,可以根据需要修改晶振频率-A countdown of the module, in seconds, you can modify the crystal frequency needed
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-31
    • 文件大小:820byte
    • 提供者:phil
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