资源列表
NonPipelined_Design
- 用VHDL实现的非流水线CPU设计，可以稍加改动变成流水线设计-VHDL implementation with non-pipelined CPU design
PipelinedCPU
- 用Verilog语言实现的流水线CPU设计，大家可以参考一下。-Using Verilog design language of the line CPU, you can reference.
clock
- 多功能数字钟，VHDL语言编写；是EDA学习中常见问题-CLOCK
digitalcymometer
- 基于VHDL的数字频率计，通过硬件实现，效果很好 -digital cymometer design based on vhdl language
trafficlight
- 交通灯的设计，基于quartusII软件，硬件上已实现-traffic light based on quartusII
decoder38
- 基于vhdl的38译码器的实现，很实用的示例程序，物理可实现-decoder 38 based on quartusII
3fenpin
- 3分频的程序，很新鲜的思维，保证好用啊，奇数分频-divide frequency by 3 based on quartusII
dianziqn
- 电子琴的代码，可以自己即兴演奏的电子琴，基于vhdl语言实现，音色很不错啊-e-piano based on quartusII and designed by vhdl language
FSK_VHDL
- FSK调制与解调VHDL程序及仿真,基于VHDL硬件描述语言，对基带信号进行FSK调制-Modulation and demodulation FSK VHDL procedures and simulation
quartus_ii_tutorial_hierarchical
- quartus guide book for verilog
quartus_ii_tutorial
- quartus- II tutorial
CPU_data_path_design_is_very_simple
- 居于硬件描述语言的简单CPU设计，能够实现比较简单的数据传送处理功能，虽然功能简单，但只要搞懂了其中原理，对于大的系统就能够有依葫芦画瓢的强大效果。-Living in a simple CPU hardware descr iption language design, to achieve relatively simple data transfer processing functions, although the functionality is simple, but as lon