资源列表
VPR_HET
- 用于学术研究的FPGA布局布线软件VPR
modelsim6.2b
- 使用Modelsim进行仿真，包括前仿真，与后仿真，使用Quartus 调用Modelsim进行仿真-Using Modelsim simulation, including the former emulation, and after the simulation, the simulation using Quartus call Modelsim
traffic
- 交通灯 vhdl 进程
maxshiyan
- 大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等，此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital d
s3ansk_paint
- Paint for SPARTAN 3E
BCD_subtracter
- VHDL编写的7位BCD减法器，可实现带小数点减法运算。-VHDL, 7 BCD subtraction, which can be achieved with a decimal point subtraction.
lcd1602_ise7_bak
- THIS CODE VERY GOD FOR DRIVE LCD2X16 THISE CODE IS TESTED CRYSTAL 40MHZ RESET VERY IMPORTANT KEY IN THIS PROGRAM
rfid_re
- VHDL实现 DDS。大家共享吧，一起学习，一起进步
Whac-A-Mole
- VHDL语言打地鼠小游戏，包含整个工程和仿真波形。-VHDL language playing hamster games, and include the entire engineering simulation waveform.
ppq1
- 高教杯&xilinx 北京市题目 我们自己出来的，全部符合要求-Higher Cup & xilinx subject ourselves out of Beijing, all to meet the requirements
TestMachine
- VHDL source code for test machine.
1076 IEEE Standard VHDL Language Reference Manual.
- 1076-2002 IEEE Standard VHDL Language Reference Manual-1076-2002 IEEE Standard VHDL Language Ref validated Manual