资源列表
teacher_uart
- 由verilog编写的uart收发模块，能够在串口助手发送字符，并在数码管上显示，开发板为basys3 内置约束文件(The UART transceiver module written by Verilog can send characters to serial assistant and display them on the digital tube. the development board is built-in constraint file of basys3)
m_decode
- 关于ISO18000-6c协议中反向链路的编码实现没有最终调通-failed to translate
video_monitor
- 基于FPGA的便携式防盗监控系统的设计与实现-Design and implementation of FPGA-based portable security monitoring system
DE2_USB_API
- altera d2e usb api example
512MbDDR2
- DDR2的用户手册，需要的同学可以下载，在实际应用中很重要-DDR2 user manual, students need to be downloaded, it is important in practical applications
DDS
- 在MAXPLUSII下开发的基于verilog的直接数字频率合成器-Developed under the MAXPLUSII verilog-based direct digital frequency synthesizer
vmm_golden_reference_guide_jan_2010
- 搭建基于vmm架构验证环境的黄金指导手册.-vmm golden reference guide
vmm_golden_reference_guide_jan_2010
- advanced vhdl guide (ovm)
Timer
- 计时器的设计，在Quartus II上运行通过，FOR NJU Cser。使用了signaltap-The design of the timer, run by the Quartus II, FOR NJU Cser. Used signaltap
LATTICE_ASYNFIFO
- LATTICE FPGA FIFO 程序例程，工程详细，全部源代码上传 -LATTICE FPGA FIFO routine, detailed engineering, all source code uploaded
Lec1_intro_f09
- FPGA design base element
IS_7985MA_INX56_080825_F
- This File Mstar Processer -This is File Mstar Processer