资源列表
Verilog
- Verilog数字系统设计教程夏宇闻例题源文件-Verilog Digital System Design Education Chengxia Yu Wen example source file
Synplify_Pro_FPGA
- 基于 Synplify /Synplify Pro 的 FPGA 高级综合设计-Based Synplify/Synplify Pro advanced FPGA synthesis design of
VHDL_learning
- VHDL学习资料，适合入门者快速提高，包括VHDL基本语句讲解，VHDL编程黄金宝典和100个VHDL设计范例。-VHDL learning materials, suitable for beginners to quickly improve, including statements to explain the basic VHDL, VHDL programming, and 100 Gold Collection VHDL design examples.
DDR2_controller
- DDR2控制器IP的设计与FPGA实现，使用verilog语言-DDR2 Controller IP Design and FPGA implementation, use the verilog language
easy_to_modelsim
- 这里包含6个modelsim的学习资料，包括了经典教程、答疑和分别针对VHDL、Verilog语言的仿真例程。-This contains six modelsim of learning materials, including the classic tutorial, tutorials, and were aimed at VHDL, Verilog simulation language routines.
the_design_and_realization_of_DDR2-SDRAM_controlle
- ddr2控制器的设计与实现,详细介绍了其结构和思想-the design and realization of DDR2-SDRAM controller
DDRSDRAM_DDR2SDRAM_controller
- 适用于DDRSDRAM和DDR2SDRAM的控制器的设计-Applicable DDRSDRAM and DDR2SDRAM the controller design
8w64fb
- 8位64个采样点的方波发生信号器。基于PFGA的采用PLL模块实现功能-8 of 64 samples of signal square wave device. The use of PLL-based PFGA module function
EDAdianzizhong
- 基于FPGA的数字电子钟设计，有VHDL语言实现其功能-FPGA-based design of digital electronic clock with VHDL language function
EDA
- 熟练使用vhdl语言，以及介绍了quartus和仿真软件，具体事例-Vhdl skilled use of language, and introduced quartus and simulation software, specific examples
sseg
- vhdl codefor 7 segment display
hdbn
- HDBN VHDL Project includes hdb3 & hdbn