资源列表
ModelSim
- verilog Source code for DCT
FPGAmarket
- 消费类产品是未来PLD_FPGA市场的增长点，讲述FPGA的市场前景-Opportunities and challenges Xilinx FPGA on the future direction and trends
FPGAfuture
- 机遇与挑战并存Xilinx谈FPGA未来的发展方向及趋势-Opportunities and challenges Xilinx FPGA on the future direction and trends
std_logic_unsigned
- 一组符号arithemtic、转换,并比较STD_LOGIC_VECTOR功能的程序包。-A set of unsigned arithemtic, conversion, and comparision functions for STD_LOGIC_VECTOR.
std_logic_signed
- 一套签署arithemtic、转换、及比较STD_LOGIC_VECTOR功能的程序。-A set of signed arithemtic, conversion,and comparision functions for STD_LOGIC_VECTOR.
std_logic_arith
- 一个用于转换设置，以及签署SMALL_INT，整数，STD_ULOGIC，STD_LOGIC和STD_LOGIC_VECTOR比较函数。-A set of arithemtic, conversion, and comparison functions for SIGNED, UNSIGNED, SMALL_INT, INTEGER,STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR.
std_logic_1164
- 这个包定义了vhdl标准,为设计者在使用数据类型时建立用于vhdl的互连模型。-This packages defines a standard for designers to use in describing the interconnection data types used in vhdl modeling.
MP3
- MP3解码的ASIC全部过程，包换含c和vhdl代码，样例。-MP3 decoding ASIC whole process, shifting with c and vhdl code, sample.
ASIC
- 本文介绍了基于标准单元库的深亚微米数字集成电路的自动化设计流程。此流程从 设计的系统行为级描述或 RTL 级描述开始，依次通过系统行为级的功能验证，设计综合，综合后仿真，自动化布局布线，到最后的版图后仿真。在-This article describes the standard cell library based on deep sub-micron digital IC design flow automation. This process from the design of sy
xge_mac_latest.tar
- Ethernet 10GE MAC 以太网10G的MAC Verilog代码实现-Ethernet 10GE MAC
FPGAdesignFAQ
- fpga设计的常用问答解释等。有一定用处。-fpga design faq for learning. it is useful .
FPGA
- FPGA硬件接口设计一书中的源码，有参考意义。-FPGA