资源列表
e1_framer
- E1 DeFramer :A design for Framing Telecom E1 Interface
I2CMaster
- 一个实现I2C控制接口的控制程序，已经通过仿真验证，并且可以直接调用了-I2C control interface, an implementation of control procedures has been verified by simulation and can be directly called
Hardware_development_VHDL8_bit_asynchronous_counte
- 硬件开发VHDL8位异步计数器一个课程设计Hardware development VHDL8 bit asynchronous counter-Hardware development VHDL8 bit asynchronous counter of a course design Hardware development VHDL8 bit asynchronous counter
McGraw_Hill_-_VHDL.Programming.by.Example.4th.Ed.
- ebook of VHDL programming for beginners
fpga_usb_serial_20091006.tar
- 免费的usb2.0源码,支持Xilinx和Alteral的FPGA-USB2.0 free sources
SD
- SD datasheet basic mini sdhc
QAM16_Demapping
- 用VERILOG写的解16qam程序。本来是针对OFDM设计的，有一定参考价值。-Solutions 16qam with VERILOG written procedures. Was originally designed for OFDM has some reference value.
fft_st
- 用NIOS2核建的FFT工程，能够对输入的数据进行FFT或IFFT变换。-FFT with NIOS2 nuclear construction projects, to input data on FFT or IFFT transform.
SPI_Bridge_Design_Example
- 基于ALTERA的nios2的SPI通信，文档包含整个工程，包括主从模式，很有参考价值。-Based on ALTERA' s nios2 the SPI communication, the document contains the entire project, including master-slave mode, a good reference.
dds
- 在quartus下的DDS设计，Verilog语言，可以产生正弦波、三角波、方波等，频率可调。-Under the DDS in quartus design, Verilog language, you can produce sine wave, triangle wave, square wave, frequency adjustable.
MCPUDESIGN
- This file is fof single Process Unit design for new pepole -This file is fof single Process Unit design for new pepole
chap3
- verilog, please download and excise-verilog,please download and excise