- checknode_VHDL ldpc check nod for vhdl
- data_manipulation 包含一些比较常见的数据操作算法：素数判断
- managingstudent vc6.0下运行的学生档案管理系统
- drawingpad 简易画图板
- bisect ion method
- AOMEI_OneKey_Recovery_Customization_1.6.2 AOMEI ONEKEY RECOVERY Customization 1.6.2 License file included(AOMEI ONEKEY RECOVERY Customization 1.6.2 License file included You can change strings
资源列表
dds
- vhdl编写，利用fpga完成了dds发生器的功能-vhdl prepared using fpga complete function generator dds
uart
- vhdl编写，完成了uart的接口设计，包括信号检测，判决等-vhdl prepared to complete the uart interface design, including signal detection, decision, etc.
ad574
- vhdl编写，完成了对ad芯片ad574的控制，并将转化的数据存于fpga的内部存储器中，然后在发送出去。-vhdl prepared, completed ad control chip ad574, and conversion of data stored in the fpga internal memory and then sent.
cpu
- fpga实现了简单的cpu，有三个指令，有加法，减法，移动三条指令-fpga to achieve a simple cpu, there are three directives, there is addition, subtraction, move three orders
fpga
- vhdl和c编写，fpga结合单片机完成测频计的功能，fpga主要完成频率的测量并把数据发送给单片机，单片机控制12864液晶完成显示-vhdl and c preparation, fpga of the single chip to complete the function of frequency meter, fpga major to complete the measurement frequency and the data sent to the MCU, MCU contro
tiaozhi
- 使用vhdl完成了ask psk fsk的调制和解调-Completed using vhdl ask psk fsk modulation and demodulation
ser_fir
- 用verilog实现一个8阶的改进串行FIR低通滤波器，输入数据位宽为12比特,经符号扩展后变为13比特。-With verilog order to achieve an improvement of 8 serial FIR low-pass filter, the input data bit width of 12 bits by sign extension into a 13-bit after.
Classic_Manual_Verilog_programming_language
- Verilog编程语言经典手册Classic Manual Verilog programming language-Verilog programming language classic manual Classic Manual Verilog programming language
Chinese_version_of_Verilog_notes
- Chinese version of Verilog notesVerilog讲义中文版-Chinese version of Verilog notesVerilog handout Chinese
Electronic_tutorials_Verilog_hardware_description_
- 硬件描述语言Verilog电子教程Electronic tutorials Verilog hardware descr iption language-Verilog hardware descr iption language tutorial Electronics Electronic tutorials Verilog hardware descr iption language
VerilogHDL_classical_information_document
- VerilogHDL classical information documentVerilogHDL经典资料文档-VerilogHDL classical information documentVerilogHDL classical information document
Verilog-code
- 国外经典VERILOG代码，学习verilog的好材料-Foreign Classics VERILOG code of good material to learn verilog