资源列表
convolution
- This the code for the convolutional and the test bench for this in the verilog code.-This is the code for the convolutional and the test bench for this in the verilog code.
equalizer
- This the code for the channel equalizer and the test bench for this in the verilog code.-This is the code for the channel equalizer and the test bench for this in the verilog code.
rs_232
- Comunication rs232 in vhdl
soma_loka
- Sum make in vhdl code
8a
- 2 Flip Flops in VHDL
VGAController
- Easy VGAController in vhdl
ExperimentoCap9
- Question cpa 9 of the an book in portuguese
Frequce
- 能测量频率，并且能测占空比10 90 ，还能产生1M 占空比10 的脉冲波- 能测量频率，并且能测占空比10 90 ，还能产生1M 占空比10 的脉冲波 Can measure the frequency, and can measure the duty cycle 10 90 , but also can produce the 1M duty cycle 10 of the pulse wave
1602verilog
- 采用Verilog语言完成了1602液晶屏的驱动显示-Using Verilog language to complete the 1602 LCD screen driver display
code_lagrange_interpolation
- 使用verilog实现拉格朗日插值，很有使用价值，有需要的可以参考一下-Use verilog to achieve Lagrange interpolation, very useful value, there is a need to refer to
FPGA_拉格朗日插值_IP
- fpga实现拉格朗日插值，本工程采用verilog语言实现，可直接使用
register
- 用Verilog实现了一个基本寄存器，并且用仿真和led灯来显示了读写数据。-Using Verilog to achieve a basic register, and led lights and simulation to show the read and write data.