资源列表
145103015
- Verilog source code for using keypad module with zybo fpga board to take input and show output to onboard leds and led module connected to GPIO
FPGA_txt
- 该源码为基于FPGA所开发的TXT文本阅读器，本模块可运用于阅读器开发的实际运用中，并且可用作FPGA开发各类阅读器的模板框架-The source code for the development of FPGA-based TXT text reader, the module can be used in the practical development of the reader, and can be used as FPGA development of various types
FPGA_Vision
- 该源码为基于FPGA的工业现场实时监控界面的设计，本模块可实际运用于FPGA工业应用场合，也可以作为FPGA设计的参考-The source code for the FPGA-based industrial real-time monitoring interface design, the module can be used in the actual application of FPGA industry applications, can also be used as a ref
pldexp3_time
- PLD实验B组实验3，LCD1602动态显示时间，verilog语言-PLD experiment B group experiment 3, LCD1602 dynamic display time, verilog language
PLD_two
- PLD实验B组第二次实验，LCD1602显示学号，verilog语言-PLD experimental group B second experiment, LCD1602 display student number, verilog language
RD1213_Video_Pipeline
- This document describes the structure and implementation of a video pipeline demo design running in the Lattice ECP3-150EA-8FN1156C device based on the Sparrowhawk FX Board. This demo takes two of the four video streams DVI and SDI inputs and the
HDMI_FPGA
- 该源码可基于FPGA设置多分辨率的HDMI显示，且其包含了完整的时序和端口、地址映射，可以很方便的将其移植-The source code can be set based on FPGA multi-resolution HDMI display, and it includes a complete timing and port, address mapping, it can be easily transplanted
HDMI_4AV
- 该源码为基于FPGA的HDMI显示的一拖四的AV视频采集。该模块可方便移植在需要使用HDMI高清显示的场合，并且可将VGA显示一分为四，方便各个窗口显示不同的图像信息-The source for the FPGA-based HDMI display of a four of the AV video capture. The module can be easily transplanted in the need to use the HDMI high-definition displa
mt9d112_ddr2
- 镁光MT9基于FPGA图像采集模块，该模块可同时采集两路视频信号。其包括完整的时序和接口、ddr2内存数据写入和存储、qsys系统的搭建、FPGA与NIOS II联合设计-Micron MT9 based on FPGA image acquisition module, the module can simultaneously capture two video signals. Including the complete timing and interface, ddr2 memory
mapperSharp1(16QAM)
- This the code for the mapper in the verilog code.-This is the code for the mapper in the verilog code.
inter_deleaver
- This the code for the interleaver and the deinterleaver in the verilog code.-This is the code for the interleaver and the deinterleaver in the verilog code.
demapperSharp1(16QAM)
- This the code for the demapper in the verilog code.-This is the code for the demapper in the verilog code.