资源列表
SPI_SD_CARD
- 使用sopc系统，结合nios软件，实现sd卡的读写，学习FPGA编写的过程-Use sopc system, combined with nios software, sd card reader, prepared by the process of learning FPGA
usb_host_device_verilog
- USB-host-device控制模块的设计参考，对于初学者可以以此为参考进行设计，代码可在仿真软件中验证（modelsim、VCS等）。-USB-host-device control module design reference for beginners can be used as a reference design, the code can be verified in the simulation software (modelsim, VCS, etc.).
dma_bridge_verilog
- DMA控制模块的设计参考，对于初学者可以以此为参考进行设计，代码可在仿真软件中验证（modelsim、VCS等）。-DMA control module design reference, for beginners can be used as a reference design, the code can be verified in the simulation software (modelsim, VCS, etc.).
uart_model_verilog
- uart通信协议的设计参考，对于初学者可以以此为参考进行设计，代码可在仿真软件中验证（modelsim、VCS等）。-Uart communication protocol design reference for beginners can be used as a reference design, the code can be verified in the simulation software (modelsim, VCS, etc.).
spi_verilog
- spi通信协议的设计参考，对于初学者可以以此为参考进行设计，代码可在仿真软件中验证（modelsim、VCS等）。-Spi communication protocol design reference for beginners can be used as a reference design, the code can be verified in the simulation software (modelsim, VCS, etc.).
QAM
- 16QAM调制 基于vivado环境下16QAM调制 -16QAM modulation
bresenham_algorithm
- This a project which contains a verilog code for Bresenham algorithm for linear interpolation, the code is tested using isim simulator.
shumaguan
- FPGA课程实验代码，基于xinlix实验开发平台的数码管显示学号完整程序，下载到实验板，测试通过。-FPGA experiment courses code, based on xinlix experimental platform of digital tube display full program student id, download to experiment board, the test pass.
miaobiao
- FPGA课程实验，基于xinlix实验平台的秒表程序实现，下载到实验板上，测试通过。-FPGA experiment, the experiment platform based on xinlix stopwatch program implementation, download to experiment, the test pass.
led_river
- FPGA实验，基于VHDL语言的流水灯程序设计，采用分模块设计思路。下载到板子上测试通过。-FPGA experiment, water lamp program design based on VHDL language, using modular design train of thought.Downloaded to the board on the test pass.
dig_watch
- fpga实验，基于VHDL语言的数字跑表设计，其中包含有存储模块。-Fpga experiment, the digital stopwatch designed based on VHDL language, which contains a storage module.
decoder_38
- FPGA实验，基于VHDL语言的一个38译码器，实测效果非常好，请各位多多指教-FPGA experiment, based on the VHDL language a decoder 38, actual effect is very good, please advice