资源列表
AudioDelay_12bit
- Experimental digital ADC and audio delay using VHDL on Spartan3E 500k
verilog-sin
- FPGA开发sin波形，用verilog写的正弦波发生器。-FPGA development sin wave with verilog write sine wave generator
lab_5
- Introduction to learn laboratry with altera quartus II 9.1
seg
- FPGA简单程序，可实现一位数码管显示，从0到9 的循环显示-FPGA simple program, enabling a digital display, the display cycles 0-9
RAM
- FPGA简单程序，RAM可读可写存储器，容易读懂-FPGA simple program, RAM readable and writable memory, easy to read
fp
- FPGA基础程序，分频器的设计及实现，利用计数器实现-FPGA based program, crossover design and implementation, realized by the counter
led
- 简单程序，led流水灯设计，基于移位操作-Simple procedures, led water lamp design, based on the shift operation
moshijishu
- FPGA基础代码，模10计数器，可实现加计数-FPGA code base mold 10 counters, counting can be achieved
VHD-L-QUARTUS--Counter
- 基于QUARTUS软件的VHDL语言开发，文件中含有VHDL语言设计的分频器，加法减法计数器，并生成有原理图，只要有QUARTUS软件即可仿真运行。-VHDL QUARTUS Counter
rate
- 一个通过降低精度提高运算速度的8bit加法器设计，仅供参考-A improve processing speed by reducing the accuracy 8bit adder design, for reference only
b4b52
- 4b5b编码器实现，初学者资源，简单的逻辑电路实现-4b5b encoder implementation, resources for beginners
ALU
- 简单在fpga上实现的alu部分功能，初学数字信号处理者使用-Simple on fpga alu implemented some functions, beginner to use digital signal processing